2019 JETTA-TTTC Best Paper Award
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2019 JETTA-TTTC Best Paper Award Breeta SenGupta, Dimitar Nikolov, Assmitra Dash and Erik Larsson, “Test Flow Selection for Stacked Integrated Circuits,” Journal of Electronic Testing: Theory and Applications, Volume 35, Number 4, Pages 425–440, August 2019.
# Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract: Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips - 3D Stacked ICs there are many possible test instances, even more test flows, and no commonly used test flow. In this paper, we propose a test flow selection algorithm (TFSA) to obtain a test flow for a given 3D Stacked IC. The TFSA results in a test flow for a given 3D Stacked IC, such that the expected total test time to produce each good package is minimized. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three different test architecture design approaches. The results demonstrate the importance to have methods both to select the test flow and design the test architecture.
Breeta SenGupta received her M.Sc. from Indian Institute of Technology, Kharagpur, India, in 2009 and Ph.D. at the Department of Electrical and Information Technology, Lund University, Sweden in 2020. Her area of research includes 3D integration, design for test and test optimization. At present,
Breeta is employed at Ericsson, Sweden for test development and mixed signal verification of RF ASICs.
Dimitar Nikolov received the diploma engineering degree from SS. Cyril and Methodius University, Skopje, Macedonia, in 2008, the licentiate degree from Linköping University, Linköping, Sweden, in 2012, and the Ph.D. degree from Lund University, Lund, Sweden, in 2015. From 2015 until 2017, he was a postdoc fellow with Lund University working on research topics that included fault tolerance, design and test of digital systems, computer architectures, reconfigurable computing, and digital signal processing. He has reviewed papers submitted at the IEEE Transactions on Computers, the IEEE Transactions on Very Large Scale Integration Systems, and has been a program committee member for the Workshop on RTL and High Level Testing (WRTLT) 2016. He has received the best paper award at the IEEE European Test Symposium 2016. Currently, he is working as an algorithm developer in Ericsson AB, Sweden.
Assmitra Dash received his M.Sc. degree from the department of Computer and Information Science from Linköping University in 2013, and is currently working as a software engineer in SAP SE.
Erik Larsson received his M.Sc., Tech. Lic and Ph.D. from Linköping University (LiU) in 1994, 1998, 2000, respectively. After a Post Doc (2001–2002) at Nara Institute of Science and Technology (NAIST), Japan, he was with LiU as Assistant
Professor (2002–2005) and Associate Professor (2006– 2012). Since 2012 he is with Lund U
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