A Comparative Study on the Activation Behavior of Implanted Boron and Phosphorus for LTPS Using Solid-Phase Crystallizat
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A Comparative Study on the Activation Behavior of Implanted Boron and Phosphorus for LTPS Using Solid-Phase Crystallization Qinglong Li1, Tarun Mudgal1, Patricia M. Meller1, Seth Slavin1, Robert G. Manley2 and Karl D. Hirschman1 1 Department of Electrical and Microelectronic Engineering, Rochester Institute of Technology, 82 Lomb Memorial Drive, Rochester, NY 14623 2
Science and Technology Division, Corning Incorporated, SP-PR-02, Corning, NY 14831
ABSTRACT This work presents a study on the activation behavior of high-dose (I > 1015 cm-2) boron and phosphorus implants for low resistance source and drain regions for thin-film transistors (TFTs) fabricated using solid-phase crystallization (SPC) of amorphous silicon. Process variables include factors associated with ion implant and annealing conditions, as well as the SPC and implant process arrangement. Four-point probe sheet resistance (Rs) measurements were used as a comprehensive assessment of the electrical properties. Results have identified similarities and differences in activation behavior that can influence process integration strategies considering both the SPC approach and TFT fabrication. INTRODUCTION Low-temperature polysilicon (LTPS) has emerged as a dominant technology for high performance TFTs used in mobile LCD and OLED display products. Most of the current LTPS technology utilizes excimer-laser annealing (ELA) of a-Si [1, 2], however there are challenges in scaling ELA techniques for backplane manufacturing on large glass panels. Solid-phase crystallization (SPC) offers an alternative method of forming LTPS without the limitations and complexity of ELA [3-6]. Recent interest in using LTPS for large-format displays has provided the motivation to develop process enhancements for improved SPC-LTPS transistor performance. Ion implantation is typically used for boron and phosphorus dopant introduction in top-gate LTPS for self-aligned source/drain implants. This work presents an investigation on SPC-LTPS using boron and phosphorus ion implantation and furnace annealing processes. EXPERIMENT Substrate preparation involved the deposition of hydrogenated amorphous silicon (a-Si:H) using a PECVD process on 150 mm diameter Corning EAGLE XG® display glass wafers with a 100 nm SiNX barrier layer and a 250 nm SiO2 buffer layer. The deposition was performed using SiH4 and H2 at 400 °C, 1 Torr pressure and 30 W RF power. Deposition time was adjusted to provide silicon film thicknesses (XSi) of either 60 nm or 100 nm. A dehydrogenation anneal was then done at 450 °C for 2 hours at 200 mTorr. The experiments were divided into two parts. Part-I was designed to investigate the influence of the implant and anneal process arrangement on the activation of heavily doped boron and phosphorus, and Part-II was a refined experiment to further the investigation on the influence of the impurity concentration profile within the deposited silicon layer.
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The first part of the experiment investigated the implant and annealing process arrangement. Prepared samples were impl
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