A flipped-voltage-follower-based low-dropout regulator with signal- and transient-current boosting
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A flipped-voltage-follower-based low-dropout regulator with signaland transient-current boosting Yuet Ho Woo1 • Koi Shu Ho1 • Yajun Lin1 • Yong Zhou1 • Ka Nang Leung1 • Yanqi Zheng2 Jianping Guo3
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Received: 3 September 2019 / Revised: 23 January 2020 / Accepted: 26 September 2020 Ó Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract A flipped-voltage-follower-based low-dropout regulator (FVF-LDO) with signal- and transient-current boosting (STCB) is proposed in this paper. The embedded STCB structure to FVF-LDO enhances both loop gain and loop bandwidth, while the FVF-LDO remains its double-pole single-zero property within the loop bandwidth and can be stabilized by an external output capacitor to achieve dominant-pole frequency compensation. The proposed LDO designed in a 65-nm CMOS technology operates at a minimum of 1 V, provides an output of 0.85 V, and delivers a maximum of 50 mA. The figure-ofmerit of proposed FVF-LDO is 1.98 ps. Keywords Line transient response Load transient response Loop gain Low-dropout regulator Power-supply rejection ratio Signal- and transient-boosting
1 Introduction Conventional low-dropout regulator (LDO) has an error amplifier which compares the scaled output voltage with a supply- and temperature-insensitive reference voltage to generate an error voltage to adjust the source-to-gate voltage of power PMOSFET to deliver different outputcurrent levels [1–6]. The speed and gain of the error amplifier significantly affects the accuracy and transient response of LDO. In recent years, there are many designs adopting different circuit methods to improve transient response. Some designs focus on power-PMOSFET-size reduction to decrease the gate capacitance for speed enhancement [1]. There are other designs using adaptive biasing, such that the bias current for the error amplifier & Yanqi Zheng [email protected] 1
Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong, People’s Republic of China
2
School of Electronic and Information Engineering, South China University of Technology, Guangdong, China
3
School of Electronics and Information Technology, Sun YatSen University, Guangzhou, China
can be increased momentarily to improve both small- and large-signal responses [3]. Some designs are concentrated on the overall loop-gain response, and hence frequency compensation topology for LDO becomes vital [4–6]. In 2005, a simplified LDO structure based on flipped-voltage follower (FVF) was reported, as shown in Fig. 1 [7], in which a single transistor acts as the input stage of error amplifier, such that the LDO circuit structure becomes simple and fast. The frequency and transient responses have been investigated in detail in [8]. This FVF-based LDO (FVF-LDO) can be stabilized with or without a large off-chip output capacitor. When the output capacitor is absent, the transient response can be enhanced by a capacitive-coupling dynamic biasing method proposed in [9]. For the accuracy of FVF-LDO, it has a strong relation
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