A Fully Automated Environment for Verification of Virtual Prototypes
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A Fully Automated Environment for Verification of Virtual Prototypes P. Belanovi´c, B. Knerr, M. Holzer, and M. Rupp Institute of Communications and Radio Frequency Engineering, Vienna University of Technology, 1040 Vienna, Austria Received 15 October 2004; Revised 29 March 2005; Accepted 25 May 2005 The extremely dynamic and competitive nature of the wireless communication systems market demands ever shorter times to market for new products. Virtual prototyping has emerged as one of the most promising techniques to offer the required time savings and resulting increases in design efficiency. A fully automated environment for development of virtual prototypes is presented here, offering maximal efficiency gains, and supporting both design and verification flows, from the algorithmic model to the virtual prototype. The environment employs automated verification pattern refinement to achieve increased reuse in the design process, as well as increased quality by reducing human coding errors. Copyright © 2006 P. Belanovi´c et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
1.
INTRODUCTION
Complexity of modern embedded systems, particularly in the wireless communications domain, grows at an astounding rate. This rate is so high that the algorithmic complexity now significantly outpaces the growth in complexity of underlying silicon implementations, which proceeds according to the famous Moore’s Law [1]. Furthermore, algorithmic complexity even more rapidly outpaces design productivity, expressed as the average number of transistors designed per staff/month [2, 3]. In other words, current approaches to embedded system design are proving inadequate in the struggle to keep up with system complexity. Hence, a number of new system design techniques with potential to speed up design productivity are intensively researched [4, 5]. One of these techniques known as virtual prototyping [6–8] speeds up the design process by enabling development of hardware and software components of the embedded system in parallel. Development of a comprehensive design environment for automatic generation and verification of virtual prototypes (VPs) from an algorithmic-level description of the system is presented here. Section 1.1 describes the concept of a VP in closer detail and Section 1.2 explains the model of the hardware platform used in this work. A survey of related work, including a comparison of the presented environment with the most advanced current approaches, is given in Section 1.3. The design environment for automatic generation of VPs is described in detail in Section 2. The part of
the presented environment concerned with automated verification pattern refinement for VPs is presented in Section 3, together with an example design. Finally, conclusions are drawn in Section 4. 1.1.
Virtual prototype concept
System descriptions at algorithmic level contain no specific
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