A game theory approach for RTL security verification resources allocation
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A game theory approach for RTL security verification resources allocation Haoyi Wang1 · Yici Cai1 · Qiang Zhou1 Received: 7 June 2020 / Accepted: 15 October 2020 © China Computer Federation (CCF) 2020
Abstract Many Trojan detection technologies are too time-consuming to cover the entire state space in complex designs. The valuable verification resources should be allocated to regions vulnerable to security threats. However, there are few studies on security verification resources allocation. To fill in this gap, we design a security game framework to guide the security verification resources allocation. The framework utilizes the Trojan vulnerability measurement as player utilities, so the utility value determination doesn’t need any expert prior knowledge to the specific design under test. A new Stackelberg security game specific to hardware security is also proposed. The new game model minimizes the defender utility loss with the limited verification resources restriction. Due to the lack of study on RTL Trojan vulnerability measurement, we also propose a RTL security vulnerability measurement to measure each logic propagation path vulnerability quantitatively and efficiently. We apply the proposed Stackelberg security game framework to Trust-hub Trojan benchmarks written by Verilog RTL code. The experiments demonstrate that the most suspicious logic propagation path is one part of Trojan in most cases and the proposed RTL security vulnerability measurement is effective. Also, the allocation strategy calculated by security game could get security confidence as high as possible with all available resources and may also cover the Trojan even when the carefully design Trojan evade the vulnerability measurement. Keywords Hardware Trojan · Verification resource allocation · Game theory · RTL security vulnerability
1 Introduction Hardware Trojans (HTs) are identified as one of the major concerns of Integrated Circuits (ICs) designers. Attackers could maliciously and intentionally modify a IC design by inserting HTs resulting in undesired behavior (Xiao et al. 2016; Li et al. 2016). HTs may change the IC functionality, leak sensitive information or even cause Denial of Service. Many HTs detection technologies (e.g. information flow analysis (Hu et al. 2018), logic testing (Dupuis et al. 2018) and formal methods) are too time-consuming to cover the entire state space in complex designs. Security verification * Haoyi Wang [email protected] Yici Cai [email protected] Qiang Zhou [email protected] 1
Department of Computer Science and Technology, Tsinghua University, Beijing 100091, China
resources, are the factor related to the security coverage of verification result, like the verification time, the sophistication of the methods, or the dedicated verification engineers available. Limited security verification resources is common today for the sake of IC development cost and time-to-market and prevent complete security coverage at all times. The valuable verification res
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