A Market Data Feeds Processing Accelerator Based on FPGA
Market data feeds present the current state of the financial market to the customers, with the demand of fast transmission and instant response. The OPRA format with the FAST protocol is one of the most widely-used formats of the market data feeds. This p
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Abstract. Market data feeds present the current state of the financial market to the customers, with the demand of fast transmission and instant response. The OPRA format with the FAST protocol is one of the most widely-used formats of the market data feeds. This paper provides an accelerator based on FPGA for processing the market data feeds in OPRA format. The accelerator focuses on encoding and decoding the data feeds concerning five of the most important categories, namely categories a, d, k, q and N. Since each OPRA block may have various possibilities of components, which have different lengths, so the latency of our design varies. Under extreme conditions, the encoder portion has the minimum latency of 72 ns and the maximum latency of 424 ns, while the decoder portion has the minimum latency of 48 ns and the maximum latency of 344 ns. Keywords: FPGA-based, market data feeds handler, low-latency.
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Introduction
Financial market data feeds refer to the messages of financial market current state that the exchanges provided for customers, which include stock prices, trades, and other related information. In modern society, the amount, sphere and speed of various financial products are increasing evidently. Meanwhile, the customers would be in superior positions when making critical decisions if they could receive those financial messages in time, and better for earlier. As the consequence, to process the financial data in an efficient way is of great significance. A low-latency market data feeds handler is desired. Today, the feeds handler are mainly based on software systems. In early 2012, the primary architectures of 55% handlers are based on software, those of 36% are based on hardware and those of 9% are hybrid.[1] However, the speed of such handler based on software system is highly influenced by the hardware that it runs on. Usually, it takes a relatively longer period of time for software-based market data feeds handler to process these data. So, pure softwarebased handler will not be a solution for the desire of low-latency. W. Xu et al. (Eds.): NCCET 2013, CCIS 396, pp. 44–52, 2013. © Springer-Verlag Berlin Heidelberg 2013
A Market Data Feeds Processing Accelerator Based on FPGA
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As for the hardware, there are typically 3 kinds of techniques used for accelerators. One is Field Programmable Gate Array (FPGA), another is Graphics Processing Unit (GPU), and the rest is Application Specific Integrated Circuit (ASIC). FPGA is a very attractive choice for accelerators. It is easy to reprogram an FPGA and to reconstruct a hardware system. The low power and space requirements are also advantages of the FPGA. To construct a system on FPGA, people should write the program in Hardware Description Language (HDL). The sophistication of such program in HDL is the main disadvantage of FPGA. GPU pays attention to the calculations of floating-point numbers. It has remarkable performance in the task with abundant such calculations. ASIC has many similar advantages as FPGA in many aspects, such as high speed, lo
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