A Nanodamascene Process to be used as a Building Block for Nanodevices
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0961-O10-07
A Nanodamascene Process to be used as a Building Block for Nanodevices Christian Dubuc, Jacques Beauvais, and Dominique Drouin Department of Electrical Engineering, University of Sherbrooke, 2500 boul. de l'Universite, Sherbrooke, Quebec, J1K 2R1, Canada
ABSTRACT We report a single-electron transistor concept and its related process enabling the fabrication of ultrasmall junction capacitance. The method utilizes a nanodamascene approach where trenches in silicon oxide are covered with a filling material and planarized with chemical mechanical polishing. Single-electron transistors fabricated with this approach were characterized up to 433 K and demonstrated that the nanodamascene process has high resolution, is relatively simple and is highly scalable.
INTRODUCTION Single electron transistors (SETs) have been around for more than two decades and their potential as extremely high density devices has already been established as well as their unique characteristics for niche markets [1-2]. The current modulation in SETs is linked to variations of the carrier tunneling rate which itself depends on the change of the charging energy EC of the system. This energy EC is defined here by e2/C, where e is an elementary charge and C is the total SET capacitance. In order to observe Coulomb blockade and a transistor effect, EC needs to be much higher than the thermal fluctuations kBT of the system, driving the need for very small junction capacitance. The fabrication of the SETs nanoscale junctions is thus a critical challenge to their large scale integration. In this work, we have developed an approach to fabricate ultrasmall junctions based on a nanodamascene method. The technique is relatively simple and allows for self-aligned junction formation. The approach is demonstrated with metallic SETs with Ti/TiOx junctions. The SETs fabricated with the nanodamascene process showed a high operating temperature range similar to other conventional transistors.
EXPERIMENT The primary objective of the nanodamascene process is to fabricate very small junctions with good controllability. This means that the number of junctions to be created, their location and their dimensions should be known very accurately. To achieve this goal, the process was designed to be self-aligned with the junction dielectric obtained by thermal oxidation. This approach ensures that no alignment errors will create junction overlap that will increase the total capacitance. Thermal oxidation is a proven method to get stable and repeatable dielectric thickness. The fabrication process begins with high resolution patterning on a silicon wafer
coated with a thermally grown SiO2 layer. We have selected an electron beam lithography (EBL) process that does not use organic resist for patterning. Inorganic layers like SiO2 are good candidates for sub 10 nm imaging [3] and can also serve as the base material for chemical mechanical polishing (CMP) [4]. Using oxide direct writing can thus save a few fabrication steps because there is no need for a photores
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