A novel polymer technology for underfill

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A novel polymer technology for underfill Osamu Suzuki*1, Toshiyuki Sato*1, Paul Czubarow*2, David Son*3 1 Namics Corporation 3993 Nigorikawa, Kita-ku, Niigata-City 950-3131, Japan E-mail [email protected], TEL +81-25-278-6600 *2 eM-TECH, Inc., *3 Department of Chemistry, Southern Methodist University, Dallas, Texas Abstract Capillary type underfill is still the mainstream underfill for mass production flip chip applications. Flip chip packages are migrating to ultra low-k, Pb-free, 3D and fine pitch packages. Underfill selection is becoming more critical. This paper discusses the performance and potential of underfills using a novel organic-inorganic hybrid polymer technology. Compared to eutectic and high lead solder, tin-silver-copper solder has lower C.T.E., higher elasticity and greater brittleness. In light of these properties, it is generally better to select high Tg and lower CTE underfill in order to prevent bump fatigue during reliability testing. Given the brittleness of low-k dielectric layers of flip chips, the destruction of low-k layers by stress inside the flip chip packages has become a major issue. Underfills for low-k packages should have low stress, and the warpage should be small. It is expected that as the low-k trend expands, the underfill is required to provide less stress. Low Tg underfill shows lower warpage. New chemical technologies have been developed to address the needs of underfills for low-k / Pb-free flip chip packages, specifically organic-inorganic hybrid polymer compounds. The organic-inorganic hybrid polymer provides excellent cure properties which enable a balanced combination of low stress and good bump protection. The material properties of the underfill were characterized using Differential Scanning Calorimetry (DSC), Thermo-Mechanical Analysis (TMA), and Dynamic Mechanical Analysis (DMA). A daisy-chained test vehicle was used for reliability testing. A detailed study is presented on the underfill properties, reliability data, as well as finite element modeling results. Introduction In a traditional approach for semiconductor package materials, it is important that the other associated components have similar expansion coefficients to prevent the build-up of thermal stresses during operation. As we have observed, better product lifetimes of electronic flip-chip packaging can be obtained on solder joints by ensuring that the CTE values of the solder and the underfill are identical. The most difficult challenge is the new requirement to protect the very fragile, low-k dielectric layers in the chip. [1] Crack prevention properties are generally in opposition of traditional target properties that provide robust bump fatigue life.[2] Underfill materials present the significantly challenging task of maintaining bump protection while ensuring ultra low-K (ULK/ELK) integrity for flip chip plastic ball grid array (FCPBGA) packaging. Technology nodes with increasingly smaller integration scales generally introduce more brittle materials and stricter design constraints, therefore signific