A resource-efficient priority scheduler for time-sensitive networking switches
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A resource‑efficient priority scheduler for time‑sensitive networking switches Zonghui Li1 · Hai Wan2 · Yangdong Deng2 · Ke Xiong1 · Xiaoyu Song3 Received: 27 February 2020 / Accepted: 3 July 2020 © China Computer Federation (CCF) 2020
Abstract Time-sensitive networking (TSN) supports the integration of standard Ethernet and industrial control networ k by providing differential quality of service (QoS). A priority scheduler is typically the central component of TSN switches for QoS. Furthermore, TSN must deal with various requirements from various domains. As a result, an FPGA-based solution becomes one of the most promising solutions for TSN switches due to its programmability and customizability. But, resource usually becomes a bottleneck in such a solution. This study proposes a flattened-priority approach to develop a new resource-efficient priority scheduler called f-iSLIP by converting the widely used nonpriority scheduler, iSLIP. We implement f-iSLIP in our TSN switches and compare it with previous priority schedulers. It reduces the resource cost of lookup tables (LUTs) by 30–50% on average and the logic latency by 20–30% on average. Moreover, the throughput tests demonstrate that it prefers high priorities with no performance loss. Keywords TSN · f-iSLIP · FPGA · Industrial ethernet
1 Introduction Industrial Ethernet Decotignie (2005), Felser (2005), Decotignie (2009), Felser (2010) contains a variety of solutions to unify industrial control networks Galloway and Hancke (2013) and standard Ethernet. To standardize * Ke Xiong [email protected] Zonghui Li [email protected] Hai Wan [email protected] Yangdong Deng [email protected] Xiaoyu Song [email protected] 1
Beijing Key Laboratory of Transportation Data Analysis and Mining, School of Computer and Information Technology, Beijing Jiaotong University, Beijing 100044, China
2
Software School, Tsinghua University, Beijing 100084, China
3
Department of Electrical and Computer Engineering, Portland State University, Portland, OR, USA
Industrial Ethernet and accelerate its development, the IEEE TSN group has been working on extending the IEEE 802.3 Ethernet standard for mixed-criticality transmission Lo Bello and Steiner (2019) since 2012. TSN orients industrial control and thus needs to satisfy various application-specific requirements such as for cars, trains, and so on. So, FPGAbased switch design Li et al. (2020) has emerged as one of the most competitive candidate solutions for TSN because of the programmability and customizability of FPGAs. However, resource usually becomes the bottleneck of such FPGA-based TSN solutions. For example, the high-level FPGA, Xilinx Virtex-7 XC7VX485T FPGA Xilinx (2016) has only 0.3 M LUTs but only standard Ethernet 802.3 is complex enough for resource cost, let alone supporting mixed-criticality transmission for industrial control networks. Resource-efficient design for TSN switches is especially important. Mixed-criticality transmission depends on priority scheduling in TSN switch
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