A Robust Process for Ion Implant Annealing of SiC in a Low-Pressure Silane Ambient
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A Robust Process for Ion Implant Annealing of SiC in a Low-Pressure Silane Ambient S. Rao,1 S.E. Saddow, 1 F. Bergamini,2 R. Nipoti,2 Y. Emirov, 1 and Anant Agrawal 3 1 2
Electrical Engineering, Univ. of South Florida, Tampa, FL 33620, USA CNR - IMM Sezione di Bologna, via Gobetti 101, I-40129 Bologna, Italy 3 Cree, Inc., 4600 Silicon Drive, Durham, NC 27703, USA Abstract
High-dose Al implants in n-type epitaxial layers have been successfully annealed at 1600°C without any evidence of step bunching. Anneals were conducted in a silane ambient and at a process pressure of 150 Torr. Silane, 3% premixed in 97% UHP Ar, was further diluted in a 6 slm Ar carrier gas and introduced into a CVD reactor where the sample was heated via RF induction. A 30 minute anneal was performed followed by a purge in Ar at which time the RF power was switched off. The samples were then studied via plan- view secondary electron microscopy (SEM) and atomic force microscopy (AFM). The resulting surface morphology was step- free and flat. 1. Introduction The mechanical strength of Silicon Carbide does not permit introduction of dopants by diffusion, as dopant diffusion in SiC is slow and requires very high temperatures [1]. Thus ion implantation of dopants in SiC has been demonstrated to be ideally suitable because of the possibility to accurately control the dopant concentration and the thickness of the implanted region without any chemical or thermodynamic constraints [2]. However implantation causes significant lattice damage and most of the implanted ions reside at the interstitial sites resulting in poor electrical activity [3]. The damage can range from point defects caused by single atom displacements at low ion doses to amorphization at high dose rates. Thermal annealing normally performed after ion implantation processing serves the dual purpose of removing defects and activating dopants, but may result in surface damage due to the high temperatures needed in SiC [refs]. For the electrical activation of p-type implanted dopant temp erature in excess of 1600°C are required [2]. One possible consequence of such a high temperature annealing of SiC is the step bunching issue that concerns the surface morphology of the sample [1,4]. At such elevated temperatures the SiC crystal surface may decompose due to selective out-diffusion of Si from the SiC lattice leading to severe degradation in surface morphology which is well known [5]. Hence some means to permit high temperature annealing of SiC implants while suppressing the out-diffusion of Si from the surface is required. Several approaches have been performed in this field but with limited success [5, 6]. In this paper preliminary implant anneals performed using silane overpressure in a CVD reactor are presented and are compared with Ar only anneals. Variations in surface morphology caused by hightemperature post-annealing have been observed using the atomic force microscopy AFM and the secondary electron microscopy SEM. The electrical properties of the implanted regions are curre
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