A simulation framework for modeling charge transport and degradation in high-k stacks
- PDF / 1,002,958 Bytes
- 8 Pages / 595.276 x 790.866 pts Page_size
- 72 Downloads / 154 Views
A simulation framework for modeling charge transport and degradation in high-k stacks Luca Larcher · Andrea Padovani · Luca Vandelli
Published online: 13 November 2013 © Springer Science+Business Media New York 2013
Abstract In this paper we present a comprehensive physical model that describes charge transport and degradation phenomena in high-k stacks. The physical mechanisms are modeled using a novel material-related approach that includes in a self-consistent fashion the charge transport (dominated by defect-assisted contribution), power dissipation and temperature increase, defect generation, and ion and vacancy diffusion and recombination. The physical properties of defects, which play a crucial role in determining the electrical behavior of the high-k stacks, depend on their atomistic configurations, as calculated using ab-initio methods. This simulation framework represents a powerful tool to interpret electrical characterization measurements. In addition, it can be used to optimize logic and memory device stacks thanks to its predictive statistical capabilities that allow reproducing gate current, threshold voltage increase and time to breakdown (TDDB) statistics. Simulation results performed using this simulation package are shown to reproduce accurately leakage current, Stress-Induced Leakage Current (SILC), threshold voltage shift observed during Positive Bias Temperature Instability (PBTI) stress, TDDB in various dielectric stacks. Keywords Modeling and simulation · Leakage current · Gate oxides · Dielectric reliability · Dielectric breakdown · Non-volatile memory
L. Larcher · A. Padovani (B) · L. Vandelli DISMI, Università di Modena e Reggio Emilia, Reggio Emilia, RE, Italy e-mail: [email protected] L. Larcher · A. Padovani · L. Vandelli MDLab, Saint Christophe, AO, Italy
1 Introduction THE understanding of the physical mechanisms governing the charge transport and degradation of high-k dielectric stacks is crucial for the development and optimization of electronic devices. The high-k dielectric stacks have introduced several additional issues affecting the operation and reliability of electronic devices, mainly related to their high density of defects [1–4]. Independently of the properties of the stacks (e.g. thicknesses of dielectric layers), defects (whose properties depend on their atomistic configurations) acting as active charge trapping centers play a crucial role in both charge transport and degradation phenomena. In CMOS devices the gate stack is typically comprised of a thin interfacial layer, made of a sub-stoichiometric silicon oxide, SiOx , and a thicker layer of hafnia, HfO2 , usually deposited by Atomic Layer Deposition (ALD) technique [5]. Charge trapping at defects located at the interface and in the bulk of the stack affects significantly MOSFET operations, increasing the gate leakage current, IG , and the threshold voltage, VT , and degrading the trans-conductance, gm [6, 7]. Furthermore, preexisting traps assisting the charge transport can trigger local degradation proce
Data Loading...
