A survey on optimizations towards best-effort hardware transactional memory
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A survey on optimizations towards best‑effort hardware transactional memory Zhenwei Wu1 · Kai Lu1 · Ruibo Wang1 · Wenzhe Zhang1 Received: 17 February 2020 / Accepted: 30 July 2020 © China Computer Federation (CCF) 2020
Abstract Transactional memory has been attracting increasing attention in recent years, and it provides optimistic concurrency control schemes for shared-memory parallel programs. The rapid development and wide adoption of transactional memory make this programming paradigm promising for achieving breakthroughs in massively parallel computing. There has been a large number of discussions towards transactional memory systems, which aimed at providing relatively simple and intuitive synchronization construction for shared-memory parallel programs without sacrificing performance. Hardware transactional memory (HTM) has become commercially available in mainstream processors, however, due to several inherent architectural limitations that will abort hardware transactions, such as cache overflows, context switches, hardware as well as software exceptions, etc., nowadays HTM systems come in a best-effort way, which necessitates the adoption of a software fallback path to ensure forward progress. In this paper, we survey state-of-the-art software-side optimizations for best-effort hardware transaction system, as well as several novel performance tuning techniques. Research efforts about joint usage of HTM and non-volatile memory (NVM) are also discussed. Keywords Transactional memory · Parallel programming · Concurrency control
1 Introduction Multi-core architectures gain dramatically increasing popularity in modern processors. Meanwhile, massively parallel processing has become the major trend for constructing computational systems with higher performance. As a consequence, constructing efficient synchronization mechanism to better unveil the potential performance of the multi-core processors, has become a major challenge for building parallel applications. The advancements in transactional memory provide new opportunities for parallel computing. Multiple academic and industrial fields, such as in-memory database, cloud computing, high performance computing (HPC), etc., may potentially benefit from the rapid development and wide adoption of transactional memory.
* Kai Lu [email protected] Zhenwei Wu [email protected] 1
College of Computer, National University of Defense Technology, Changsha 410073, Hunan, China
Conventionally, parallel programmers employ lock-based schemes to cope with the synchronization issues, where the programmer explicitly specify lock-protected critical sections to synchronize concurrent accesses to shared data. From the perspective of the sizes of the critical sections, lock-based schemes could be categorized into coarse-grained locking and fine-grained ones. Though coarse-grain locking is relatively straightforward, it could hardly achieves higher scalability. Conversely, find-grain locking provides improved performance, however, it is more error-prone
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