An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Est
- PDF / 2,910,246 Bytes
- 11 Pages / 600.05 x 792 pts Page_size
- 63 Downloads / 166 Views
Research Article An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation Jonne Poikonen,1 Mika Laiho,1 Ari Paasio,1 Lauri Koskinen,2 and Kari Halonen2 1 Department 2 Electronic
of Information Technology, University of Turku, 20014 Turku, Finland Circuit Design Laboratory, Helsinki University of Technology, P.O. Box 300, 02015 Espoo, Finland
Correspondence should be addressed to Jonne Poikonen, [email protected] Received 25 September 2008; Accepted 30 January 2009 Recommended by Diego Cabello Ferrer A cellular analog processor array for use in variable block-size motion estimation with a new simple method for shifting reference image data is presented. The new shift method leads to a greatly reduced number of neighborhood connections for each cell of the array, and allows for all shifts within the [8,8] search area to be performed in a single step, with simple digital controls. The new shift circuitry, together with some other cell and system level optimizations , reduces silicon area and array layout complexity, enabling faster and more efficient parallel full search motion estimation hardware. A 32 × 32 cell parallel analog test array for reference-shift with a maximum block-size of 16 × 16, as well as absolute value/quadratic processing for variable block-size analog motion estimation (AME) has been designed in a 0.13 μm CMOS technology. Copyright © 2009 Jonne Poikonen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
1. Introduction Cameras with (multi-)megapixel sensors have become ubiquitous in even relatively low-end mobile phones. While this makes good quality still imaging possible, the limited amount of memory and processing power in such a batterypowered mobile platform often prohibits the use of the best available image quality for capturing video streams; typically a considerably poorer video capture resolution is used. The strong overall trend of memory technology scaling enables the integration of increasing amounts of memory within mobile phones. However, the increase of processing power which is required for real-time processing of the video stream is considerable. An integral part of all video standards is motion estimation (ME), which can take up to 80% of the power consumption of a video encoder. For small frame sizes, the ME power consumption can be reduced through algorithmic methods, however, for megapixel resolutions these solutions are not sufficient. Without new optimized circuit techniques, the power consumption due to the motion estimation
process will grow beyond the capabilities of small batterypowered platforms. The currently applied video standards for mobile terminals (e.g., H.264) employ Block-Based Motion Estimation (BBME), and preferably variable block-size motion estimation. The most fundamental operation required for BBME is the shift of the r
Data Loading...
