An FPGA-Based Accelerated Optimization Algorithm for Real-Time Applications
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An FPGA-Based Accelerated Optimization Algorithm for Real-Time Applications Mihalis Psarakis 1
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Anastasios Dounis 2 & Abdoalnasir Almabrok 1 & Stavros Stavrinidis 2 & Georgios Gkekas 1
Received: 10 September 2018 / Revised: 15 July 2019 / Accepted: 23 January 2020 # Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Many modern applications, such as industrial control, image processing and machine learning, are based on optimization algorithms that must solve compute-intensive problems under real-time constraints taking into account real-world parameters that evolve in time. Among others, evolutionary algorithms (EAs) are increasingly used in real-time applications to solve such complex optimization problems. Moreover, Field Programmable Gate Arrays (FPGAs) have been proved an effective platform for the implementation of these algorithms satisfying real-time and low-power requirements. In this paper, we study the FPGAbased acceleration of the Big Bang-Big Crunch (BB-BC) algorithm. BB-BC is an optimization method inspired by the corresponding evolutionary theory of the universe [1]. The BB-BC method is performed in two phases: in the Bing Bang phase, similarly to other Genetic Algorithms (GAs) it generates a random population of candidate solutions, while in the Big Crunch phase it shrinks these candidates around an optimal point. It has been shown that the BB-BC method outperforms classical GA algorithms for several optimization problems in terms of convergence speed. We show that the BB-BC algorithm does not suffer from the design limitations of the classical GAs that impede the performance of their hardware-based accelerators. We propose an efficient fully pipelined design of both BB-BC phases and a parallel scheme which integrates several BB-BC pipelined engines to improve system performance. We implement the proposed FPGA-based accelerator on a Xilinx Virtex-5 development board for three different fitness functions and compare the execution time against its software counterpart (in C language) and a CUDA program running on a massively parallel computing platform (GPU). We also compare the proposed optimized FPGA architecture with an RTL design generated by a high-level synthesis (HLS) design flow. We propose an Adaptive Neuro-fuzzy Inference System (ANFIS) model for fitness function approximation method to reduce the execution latency of complex fitness functions. We also demonstrate the efficiency of the proposed FPGA architecture on an image search problem, finding the darkest pixel of a grey image. The experimental results show that the proposed approach achieves significant speedup compared to the other software versions of the BB-BC algorithm and converges much faster than a typical GA algorithm making it an ideal solution for real-time embedded applications.
* Mihalis Psarakis [email protected] Anastasios Dounis [email protected] Abdoalnasir Almabrok [email protected] Stavros Stavrinidis [email protected] Georgios Gkekas [email protected] 1
Department of Informatics, Univ
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