An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing
- PDF / 6,622,615 Bytes
- 13 Pages / 600.05 x 792 pts Page_size
- 0 Downloads / 181 Views
Research Article An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing ´ ome ´ emy ´ ˆ Dominique Ginhac, Jer Dubois, Michel Paindavoine, and Barthel Heyrman Laboratoire d’Electronique Informatique et Image (LE2I), UMR CNRS 5158, Health-STIC Federative Research Institute (IFR100), Burgundy University, 21078 Dijon, France Correspondence should be addressed to Dominique Ginhac, [email protected] Received 1 March 2008; Revised 13 June 2008; Accepted 12 November 2008 Recommended by Dragomir Milojevic A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel operators are implemented on the circuit. Each pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. A 64 × 64 pixel proof-of-concept chip was fabricated in a 0.35 μm standard CMOS process, with a pixel size of 35 μm × 35 μm. A dedicated embedded platform including FPGA and ADCs has also been designed to evaluate the vision chip. The chip can capture raw images up to 10 000 frames per second and runs low-level image processing at a framerate of 2 000 to 5 000 frames per second. Copyright © 2008 Dominique Ginhac et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
1.
INTRODUCTION
Today, digital cameras are rapidly becoming ubiquitous, due to reduced costs and increasing demands of multimedia applications. Improvements in the growing digital imaging world continue to be made with two main image sensor technologies: charge-coupled devices (CCDs) and CMOS sensors. Historically, CCDs have been the dominant imagesensor technology. However, the continuous advances in CMOS technology for processors and DRAMs have made CMOS sensor arrays a viable alternative to the popular CCD sensors. This led to the adoption of CMOS image sensors in several high-volume products, such as webcams, mobile phones, PDAs, for example. Furthermore, new recent technologies provide the ability to integrate complete CMOS imaging systems at focal plane, with analog-to-digital conversion, memory and processing [1–5]. By exploiting these advantages, innovative CMOS sensors have been developed and have demonstrated fabrication cost reduction, low power consumption, and size reduction of the camera [6–8]. The main advantage of CMOS image sensors is the flexibility to integrate processing down to the pixel level. As CMOS image sensors technologies scale to 0.18 μm processes
and under, processing units can be realized at chip level (system-on-chip approach), at column level by dedicating process
Data Loading...
