Analog Layout Synthesis A Survey of Topological Approaches
Analog Layout Synthesis: A Survey of Topological Approaches Edited by: Helmut E. Graeb Analog components appear on 75% of all chips, and cause 40% of the design effort and 50% of the re-designs. Due to increasing functional complexity of systems-on-chip,
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Helmut E. Graeb Editor
Analog Layout Synthesis A Survey of Topological Approaches
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Editor Helmut E. Graeb Technische Universit¨at M¨unchen Munich Germany [email protected]
ISBN 978-1-4419-6931-6 e-ISBN 978-1-4419-6932-3 DOI 10.1007/978-1-4419-6932-3 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2010935721 c Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Preface
Analog components appear on 75% of all chips, and cause 40% of the design effort and 50% of the design errors detected after first silicon measurements, reported EDA Weekly on March 21, 2005. Due to increasing functional complexity of system-onchips, the difficulties in analog design and the lack of design automation support for analog circuits continually increase the bottleneck character of analog components in chip design. Design methodology and design automation for analog circuits therefore is a crucial problem for future system-on-chips. Eminently critical is the layout synthesis part of the analog design flow. Although there have been a lot of very good works from universities over the years, some of which even found their way to commercial EDA tools, industrial application of analog layout synthesis is still in its infancy when it is compared to its digital counterpart! The industrial point of view even says that practicable EDA tools for analog layout synthesis did not exist. But it seems that this situation is about to change. In the face of increasing circuit complexity and high performance SoC designs, the once-sleepy analog EDA market is experiencing an increasing shift from single vendor solutions to design tool integration via alliances between many players. The attempt to create an interplatform reference, such as the Interoperable PDK Libraries (IPL) alliance, where analog layouts made with a tool can be imported error-free to different frameworks, is an example. Many EDA start-ups as well as major leaders are already announcing key automated layout tools for the analog designer intended to boost his/her productivity. In this exciting scenario, academia continues to strive for new, more efficient, and complementary approaches to this task and to the existing tools, and has recently produced
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