Analysis of Resistance Asymmetry Due to p-n Junctions in Graphene FETs
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1259-S08-04
Analysis of Resistance Asymmetry Due to p-n Junctions in Graphene FETs Kangmu M. Lee1, Lingquan Wang1, Peter M. Asbeck1 and Jeong-Sun Moon2 1 Electrical and Computer Engineering Department, University of California, San Diego, La Jolla, CA 92093, U.S.A. 2 HRL Laboratories, Malibu, CA 90265-4797, U.S.A.
ABSTRACT In this paper, the resistance of graphene p-n junctions is analyzed following a classical approach. A two dimensional device simulator was employed to determine the electric field and channel conductivity variations across p-n junctions formed in graphene FET structures. The simulated resistivity peaks at the p-n junction where the total number of carriers reaches a minimum. The p-n junction resistance varies with the applied gate voltage, Vg, for the FET, and shows saturation behavior when Vg is far from the threshold value. Simulated results show that the additional resistance due to the presence of the p-n junctions is in the range of 50-500Ωµm. For comparison, resistance of p-n junctions has been extracted from experimental data of both exfoliated and epitaxial graphene FETs, and found to have a comparable magnitude.
INTRODUCTION For graphene FETs, asymmetry in the drain current transfer characteristics has been observed with respect to the gate bias. It is important to understand this asymmetry to properly model and design future carbon based electronics. It has been proposed that the asymmetry is due to additional resistances from p-n transition regions along the channel under specific bias conditions, particularly between contact regions and the channel, arising due to the ambipolar nature of graphene conduction [1,2]. Calculations of the additional resistance have already been reported, with particular attention to circumstances where p-n transition lengths are small [3,4]. Here we provide a simple analysis of the resistance of graphene FETs with p-n junctions under conditions where transition lengths are long compared with energy and momentum relaxation lengths, as is found in many experimental FETs.
THEORY and SIMULATION METHOD We employ a two dimensional device simulator to determine the electric field and channel conductivity variations in the vicinity of the FET gate, assuming rapid electron/hole equilibration. The physically-based device simulator Atlas of Silvaco with parameters modified to describe single layer graphene was used to obtain electrostatic carrier distributions under various bias conditions. The idealized structure considered in the model is particularly
appropriate to single layer graphene (as opposed to bilayer graphene) since the absence of a bandgap is conducive to rapid electron-hole equilibration. As described in Figure 1, the device studied was a graphene FET on an SiO2 substrate; a global back gate was placed beneath the back oxide, and 0.3 µm gate/drain and gate/source gaps were used. The thickness of the top gate oxide (Tox) was 10nm. A long channel device with small drain bias condition (Vds= 10mV) was used to minimize the lateral electric field effect
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