Applications of three-dimensional LSI
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Introduction In high-density and high-performance large-scale integration (LSI), various concerns such as higher off-state and subthreshold leakage, threshold voltage variability, and large signal delay by wiring have become more serious as metal-oxide semiconductor field-effect transistors (MOSFETs) continue on the path to scaling down toward 10 nm or less.1 High off-state leakage current at zero input voltage and subthreshold leakage current at very low input voltage in MOSFETs result in high static power consumption of LSIs. A large variation in threshold voltage may cause failures in circuit operation since logic “0” and logic “1” in logic circuits are determined by it. The total wiring length significantly increases, and hence the signal delay due to wiring increases as the number of transistors in LSI increases by device scaling. To overcome these concerns, it is indispensable to introduce a new concept of heterogeneous integration in which various materials, devices, and technologies are integrated on a Si substrate. Such heterogeneous integration is easily realized by three-dimensional (3D) integration, which enables 3D heterogeneous stacking of different kinds of chips such as the compound semiconductor device chip, the photonic device chip, and the spintronic device chip on complementary metal oxide semiconductor (CMOS) chips. We call such a heterogeneous 3D LSI a super-chip.2 Heterogeneous 3D integration is especially indispensable for the future Internet of Things (IoT). IoT is expected to
tremendously increase connectedness, allowing for the transfer of a huge amount of data without requiring human-to-human or human-to-computer interaction.3 IoT has evolved from the convergence of 3D integration technologies, microelectromechanical systems (MEMS) technologies, wireless technologies, and the Internet. Low power consumption, small form factor, and multifunctionality are required for embedded devices in IoT, and heterogeneous 3D integration can address such issues. This article overviews this new heterogeneous 3D integration technology. In addition, a 3D image sensor with an extremely fast processing speed and a 3D microprocessor with a self-test and self-repair function for an advanced driving assistant system are demonstrated as typical examples of a super-chip.
Overview of 3D integration technology Several thinned LSI chips with through-Si vias (TSVs) and metal microbumps can be vertically stacked in a 3D LSI. 3D integration technology is classified into three categories based on the TSV fabrication process, namely, via-first, viamiddle, and via-last. The via-middle and back-via type vialast methods are widely used to fabricate 3D LSIs.4 In the via-middle process, deep trenches are formed by reactive ion etching (RIE) after transistor formation. After forming the oxide liner, barrier metal layer, and Cu seed layer inside the trenches, these deep trenches are filled with Cu by electroplating. Then, multilevel metallization layers are formed on the TSVs
Mitsumasa Koyanagi, Tohoku University, Japan; koyanag
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