Approximate Multipliers Using Bio-Inspired Algorithm
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ORIGINAL ARTICLE
Approximate Multipliers Using Bio‑Inspired Algorithm K. K. Senthilkumar1 · Kunaraj Kumarasamy2 · Vaithiyanathan Dhandapani3 Received: 20 January 2020 / Revised: 6 July 2020 / Accepted: 28 September 2020 © The Korean Institute of Electrical Engineers 2020
Abstract As most of the real-world problems are imprecise, dedicating a lot of hardware for precise computations is futile for lowpower applications and few applications where the precision is not of paramount importance. For such applications an imprecise computational block is sufficient if it has other performance benefits like low power and low area. We propose Constrained Cartesian Genetic Programming (CCGP), a variant of CGP to evolve lower order imprecise multipliers and further the higher order multipliers are constructed from them. Gate-level architectures for 2 × 2, 3 × 2, 3 × 3 and 4 × 4 imprecise multipliers are evolved. Also, we propose few partitioning methodologies for the construction of higher order multipliers using the evolved imprecise lower order multipliers. The constructed evolved-partitioned multiplier (EPM) of orders 8 × 8 and 16 × 16 has significant performance benefits over the existing multiplier architectures in terms of cell area and power. The circuits are synthesized using Cadence SoC E ncounter® using T SMC® 180 nm standard cell library. The 16-bit EPMs show a maximum power reduction of 33% compared to other truncated multipliers and an area improvement of 2%. Keywords Evolutionary computation · Cartesian Genetic Programming · Imprecise computation · Low power arithmetic · Recursive multiplier
1 Introduction The widely used manual methods for the simplification of Boolean expressions such as Karnaugh Maps and QuineMc Cluskey’s tabulation method may not be suitable for computer based synthesis and logic optimization. Hence we require better optimization technique for synthesizing digital circuits at the gate level and the optimization goal needs to be changed dynamically depending on the user demand. The usage of evolutionary algorithm for the synthesis and optimization of digital circuits is getting popular because the level of optimization it performs. Wide ranges * Kunaraj Kumarasamy [email protected] K. K. Senthilkumar [email protected] Vaithiyanathan Dhandapani [email protected] 1
Prince Shri Venkateshwara Padmavathy Engineering College, Chennai, India
2
Loyola-ICAM College of Engineering and Technology (LICET), Chennai, India
3
National Institute of Technology Delhi, Delhi, India
of computer-aided design (CAD) tools for logic optimization are available, but only few CAD tools concentrate on gate level optimization of the logic circuit. There are handfuls of optimization algorithms which can evolve the required functionality of the digital circuit using the available logic-gates and further optimization in other dimensions are also possible using the multi-objective optimization techniques. CGP is widely used to evolve combinational circuits and many variants of CGP a
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