Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes
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Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes F. García-Herrero · M.J. Canet · J. Valls
Received: 21 November 2011 / Revised: 13 August 2012 © Springer Science+Business Media, LLC 2012
Abstract A VLSI architecture for the generalized bit-flipping decoding algorithm for non-binary low-density parity-check codes is proposed in this paper. The tentative decoding steps of the algorithm have been modified to avoid computing and storing a matrix of dimension N × 2q , for a code (N, K) over GF(2q ), reducing its complexity with a minimal penalization of its performance, less than 0.05 dB compared with the original algorithm. The architecture was synthesized using a 90 nm standard cell library, for the (837, 723) non-binary code over GF(25 ), requiring 590220 xor gates and achieving a throughput of 89 Mbps. Additionally, it was implemented in a VirtexVI FPGA device with a cost of 4070 slices and a throughput of 44.6 Mbps. Keywords Galois field · Non-binary low-density parity-check (LDPC) codes · VLSI · Decoder
1 Introduction The non-binary low-density parity-check (NB-LDPC) codes provide an important coding gain compared to their binary counterparts and the non-binary Reed–Solomon codes. This fact makes them an interesting choice to implement the Forward Error Correction (FEC) step in digital communications and storage systems. However, the high complexity of some NB-LDPC algorithms like q-ary sum-product (QSPA) [7] F. García-Herrero · M.J. Canet · J. Valls () Instituto de Telecomunicaciones y Aplicaciones Multimedia, Universidad Politécnica de Valencia, 46730 Gandia, Spain e-mail: [email protected] F. García-Herrero e-mail: [email protected] M.J. Canet e-mail: [email protected]
Circuits Syst Signal Process
and extended min-sum (EMS) [8], has forced very-large-scale integration (VLSI) designers to look for other kinds of low complexity algorithm to derive architectures with higher speed and lower area. Among the architectures of NB-LDPC decoding algorithms that can be found in the literature, the one based on the low complexity Min-max (MM) algorithm of [9] is the most efficient in terms of speed-area ratio (efficiency parameter introduced in [9]). With a frame error rate (FER) performance degradation of 0.04 dB, compared to EMS, this decoder achieves 10 Mbps with an estimated area of 638.57k xors, for a (837, 723) code. Unfortunately, if higher throughput is required, the efficiency of this architecture is drastically reduced. Other low complexity algorithms based on bitflipping [2], symbol flipping [6], and majority-logic decodable ([17] and [3]) have been recently proposed. The most attractive one for a VLSI implementation is the majority-logic decodable proposed in [17] and the one in [3], due to its low complexity. Architectures for this kind of algorithms were presented in [16] and [10]. However, algorithms in [17] and [3] have an important limitation: they are only valid for decoding low-rate codes, so as we increase the rate of the code an early degradation in the c
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