Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit
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Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit Mamoru Ishizaka1
· Michihiro Shintani1 · Michiko Inoue1
Received: 2 March 2020 / Accepted: 1 July 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Resistive random-access memory (ReRAM) has several attractive features such as high storage density and high switching frequency with low power consumption. It is hence regarded as the most promising nonvolatile memory material. However, a memristor, which is a primitive component of the ReRAM-based memory, has much lower write endurance. Hence, an error-correcting code (ECC) circuit is indispensable for realizing reliable ReRAM storage. Accordingly, we propose a hybrid CMOS/memristor-based ECC circuit. In the proposed circuit, the blocks with high-frequency write operations are implemented using the conventional CMOS technology and the other blocks are implemented using the memristors to maintain a balance between the area overhead and reliability. Through numerical experiments, we demonstrate that the proposed ECC circuit achieves smaller area and higher reliability than the full memristor-based ECC circuits and achieves much smaller area while preserving the reliability compared with the full CMOS-based ECC circuits. Keywords Resistive random-access memory · Memristor · Crossbar array · Error-correcting code · Reliability
1 Introduction Resistive random-access memory (ReRAM) is one of the most promising materials that could replace existing memory technologies [26]. Compared with static random-access memory (SRAM) and solid-state drive (SSD) devices, which are mainstream technologies in memory storage systems, ReRAM has attractive characteristics such as high storage density and high switching operation with low power consumption. ReRAM storage contains a memristor, which is a resistive memory device, as the basic storage element. Depending on the integral of the charge flowing through a memristor, its resistance changes and stored
Responsible Editor: K. Chakrabarty Michihiro Shintani
[email protected] Mamoru Ishizaka [email protected] Michiko Inoue [email protected] 1
Nara Institute of Science and Technology (NAIST), 8916-5 Takayama-cho, Ikoma, Nara 630-0192, Japan
as resistance [6]. Although the most natural application of a memristor is the memory storage, several other applications have been studied. For instance, given that a memristor can be used as a logic element, previous works have addressed the logic synthesis for memristor-based binary logic circuit [14, 21, 22]. Memristor-based neuromorphic circuits have also been proposed in [1, 16, 17, 30], where synaptic weights are represented by the conductance of memristors. However, the long-term reliability issue of a memristor is of a concern owing to its unstable and immature fabrication technology [2, 4, 15, 18, 19, 28, 29]. According to [15], faults on memristor devices can be categorized by hard or soft, and dynamic or static, as shown in Fig. 1. A hard f
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