Atom probe tomography of nanoscale electronic materials
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Introduction Over the past decade, integrated circuit and device technology has become reliant on advanced materials and complicated three-dimensional (3D) structures that continue to shrink in size and grow in complexity (a trend that is expected to continue for years).1 Characteristic feature sizes in metal oxide semiconductor field-effect transistors (MOSFETs) commonly used in microelectronics continue to shrink in accordance with Moore’s Law, and the functional properties of the MOSFETs depend on structure, elemental distribution, and interface roughness among other factors, at the nanometer or even the subnanometer scale. The distribution of just a few individual atoms, for instance, near the gate in a fin-shaped FET (finFET)2 or adjacent to a strained SiGe layer often determines the performance of individual devices. As such, optimal metrology methods are needed to routinely measure (in three dimensions) near and at the atomic scale.3 Lord Kelvin succinctly summarized the idea behind this characterization goal, “If you cannot measure it, you cannot improve it.”4 Atom probe tomography (APT) is a mass spectrometry technique based on time-of-flight measurements that also concurrently yields 3D spatial information (see the introductory article in this issue).5–9 Current capabilities of APT, such as detecting a low number of dopant atoms in nanoscale devices
or measuring segregation at a nanoparticle interface, make this technique an important component of nanoscale metrology. In this article, we briefly review some applications of APT to nanoscale electronic materials, including transistors and finFETs, silicide contact microstructures, nanowires (NWs), and Pt nanoparticles.
Transistors and finFETs One strength of APT is its ability to identify dopant distributions within single devices in 3D. Because device performance is directly influenced by dopant homogeneity, the ability to quantify and statistically evaluate dopant distributions provides an important dimension to device characterization. For example, Figure 1a shows cross-sectional 3D atom maps of n- and p-type MOSFET specimens from 65-nm technology.10,11 This MOSFET was fabricated using the following sequence. After dopants were implanted into the channel region, the gateoxide film and doped poly-Si gate were formed. The sample was then patterned and etched by conventional lithography and dry etching. After etching, As and B atoms were implanted for a source–drain extension (SDE) in n- and p-type MOSFETs, respectively.10 Phosphorus dopants in the n-MOSFET segregate to grain boundaries in the poly-Si gate (left),12 while B dopants in the
D.J. Larson, CAMECA Instruments, Inc., USA; [email protected] T.J. Prosa, CAMECA Instruments, Inc., USA; [email protected] D.E. Perea, Environmental Molecular Science Laboratory, Pacific Northwest National Laboratory, USA; [email protected] K. Inoue, Institute for Materials Research, Tohoku University, Japan; [email protected] D. Mangelinck, Institute Materials Microelectronics Nanosciences of Provence, Nationa
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