Automatic Hardware Implementation Tool for a Discrete Adaboost-Based Decision Algorithm
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Automatic Hardware Implementation Tool for a Discrete Adaboost-Based Decision Algorithm ´ J. Miteran Le2i (UMR CNRS 5158), Aile des Sciences de l’Ing´enieur, Universit´e de Bourgogne, BP 47870, 21078 Dijon Cedex, France Email: [email protected]
J. Matas Center for Machine Perception—CVUT, Karlovo Namesti 13, Prague, Czech Republic Email: [email protected]
E. Bourennane Le2i (UMR CNRS 5158), Aile des Sciences de l’Ing´enieur, Universit´e de Bourgogne, BP 47870, 21078 Dijon Cedex, France Email: [email protected]
M. Paindavoine Le2i (UMR CNRS 5158), Aile des Sciences de l’Ing´enieur, Universit´e de Bourgogne, BP 47870, 21078 Dijon Cedex, France Email: [email protected]
J. Dubois Le2i (UMR CNRS 5158), Aile des Sciences de l’Ing´enieur, Universit´e de Bourgogne, BP 47870, 21078 Dijon Cedex, France Email: [email protected] Received 15 September 2003; Revised 16 July 2004 We propose a method and a tool for automatic generation of hardware implementation of a decision rule based on the Adaboost algorithm. We review the principles of the classification method and we evaluate its hardware implementation cost in terms of FPGA’s slice, using different weak classifiers based on the general concept of hyperrectangle. The main novelty of our approach is that the tool allows the user to find automatically an appropriate tradeoff between classification performances and hardware implementation cost, and that the generated architecture is optimized for each training process. We present results obtained using Gaussian distributions and examples from UCI databases. Finally, we present an example of industrial application of real-time textured image segmentation. Keywords and phrases: Adaboost, FPGA, classification, hardware, image segmentation.
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INTRODUCTION
In this paper, we propose a method of automatic generation of hardware implementation of a particular decision rule. This paper focuses mainly on high-speed decisions (approximately 15 to 20 nanoseconds per decision) which can be useful for high-resolution image segmentation (low-level decision function) or pattern recognition tasks in very large image databases. Our work—in grey in the Figure 1—is designed in order to be easily integrated in a system-on-chip, which can perform the full process: acquisition, feature ex-
traction, and classification, in addition to other custom data processing. Many implementations of particular classifiers have been proposed, mainly based on neural networks [1, 2, 3] or more recently on support vector machine (SVM) [4]. However, the implementation of a general classifier is not often optimum in terms of silicon area, because of the general structure of the selected algorithm, and a manual VHDL description is often a long and difficult task. During the last years, some high-level synthesis tools, which consist of translating a high-level behavioural language description into a
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EURASIP Journal on Applied Signal Processing
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