Behavior of Defects Related to Interface-Stresses in Model Submicron Soi Structures
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BEHAVIOR OF DEFECTS RELATED TO INTERFACE-STRESSES INMODEL SUBMICRON SOI STRUCTURES N.D. Theodore and C.B. Carter Department of Materials Science and Engineering, Cornell University, Ithaca, NY 14853 S.C. Arney and N.C. MacDonald School of Electrical Engineering, Cornell University, Ithaca, NY 14853 ABSTRACT The origin and propagation of defects in novel submicron SOI structures have been investigated by transmission electron microscopy. The majority of the defect configurations observed could be explained in terms of dislocations generated as a result of stresses induced by the oxidation process. Dislocations were found to propagate into the silicon along particular {1111 planes in conformity with stress-modelling. The examination of particular dislocation configurations allowed an estimation of the stresses at the silicon/ silicon dioxide interface. Defect densities were observed to depend on the geometry of the structures. INTRODUCTION The need for increasing device packing densities has led to the scaling down of silicon devices into the submicron regime. In this regime, parasitic circuit elements due to wiring and junction capacitance become significant. Isolation schemes are therefore required that can reduce these elements. A variety of Silicon-on-Insulator (SOI) isolation schemes are to be seen in literature [1-3]. Selective oxidation isolation techniques are quite well established for both bipolar and metal-oxide-silicon large-scale integration applications. Conventional local oxidation (LOCOS) [4] for instance involves the masking of active regions with a nitride film during the isolation oxidation step. A problem typical of this and similar tt~chnologies is the generation of dislocations at film edges due to high-stresses in the nitride films [5]. Several investigators have looked at the origin and behavior of dislocations arising in the course of selective oxidation of silicon films or structures [5-10]. Transmission electron microscopy (TEM) has been used occasionally in these investigations; a variety of TEM techniques are in fact available for these and similar characterization of device structures [ 11]. One possible isolation scheme involves the fabrication of silicon device-structures on an oxide layer. A recently developed technology uses selective lateral oxidation of electron beampatterned silicon islands to produce submicron-width SOI structures [12]. The quality of the resulting silicon islands is important because of the influence of structural defects on the operational viability of possible devices. In this study, TEM specimens were prepared to evaluate the defect configurations present in these structures with a view to understanding the origin and propagation of the defects. This could possibly lead to methods of defectelimination. EXPEJMENTAL The novel submicron SOI structures used for this study were prepared in the following manner. First. silicon islands 0.25 ýitm wide and 1-2 mm long were defined by electron-beam lithography. The top and side walls were next capped with silicon nitri
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