CA Based Design of Fault Detection Unit for Hierarchical Directories in Scalable CMPs
In a Chip Multiprocessors (CMPs) with large number of cores, directory size increases linearly with number of sharers. To over-come the shortcomings of flat directory structures, hierarchical directory structures are used. An insignificant fault in the sh
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Abstract In a Chip Multiprocessors (CMPs) with large number of cores, directory size increases linearly with number of sharers. To over-come the shortcomings of flat directory structures, hierarchical directory structures are used. An insignificant fault in the sharer set representation of such a directory may introduce major inconsistency throughout the system. Therefore, the current work targets detection of any faulty recording in the sharer set representation of a hierarchical directory. The solution is developed around a special class of Cellular Automata (CA) with single length cycle attractors. The CA based design ensures low cost hardware implementation as well as high-speed operation. Keywords Cache coherence
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CMPs
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Hierarchical directory
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Fault detection
1 Introduction The recent advancements in technology demand high degree of performance scaling and high speed computation. To meet these requirements, complex uniprocessors are getting replaced by multicore architecture in which multiple
S. Mukherjee ⋅ B.P. Singh ⋅ M. Chinnapureddy ⋅ C. Koley (✉) ⋅ M. Dalui Department of Computer Science and Engineering, NIT, Durgapur 713209, India e-mail: [email protected] S. Mukherjee e-mail: [email protected] B.P. Singh e-mail: [email protected] M. Chinnapureddy e-mail: [email protected] M. Dalui e-mail: [email protected] © Springer Science+Business Media Singapore 2017 K.R. Attele et al. (eds.), Emerging Trends in Electrical, Communications and Information Technologies, Lecture Notes in Electrical Engineering 394, DOI 10.1007/978-981-10-1540-3_14
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processor cores are integrated in a single chip leading to Chip Multiprocessors (CMPs). In a typical CMPs system, L1 cache is the private cache of a processor core. L2 is shared among the cores. In a shared memory system, uncontrolled access to shared data by different processor cores may introduce inconsistencies in the data states. So, all the L1 caches are required to be kept coherent with the L2 cache, both from system performance and power efficiency point of view. CMPs, implementing directory-based protocol, maintains a directory between the private and shared caches. Directory based coherence protocols can scale well for large number of processors in shared-memory based systems. It takes care of all cached copies of a shared data. However, the directory size grows linearly with increase in number of cores, making the implementation area inefficient. In hierarchical directory organizations, each level of hierarchy maintains information about their lower levels. So, energy and area grow logarithmically with increasing core count. Scalable Coherence Directory (SCD) introduced in [1], is an efficient hierarchical directory structure that scales to thousands of cores efficiently keeping exact sharer representation. But, fault-free recording of sharer information between the various levels of SCD is highly required for its proper functioning. This motivates us to design a fault detection unit for detecting f
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