Carbon nanotubes for high-performance logic
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Introduction Improving the packing density and switching speed of fieldeffect transistors (FETs) has been the main focus of complementary metal oxide semiconductor (CMOS) computing for decades. It is well understood that both can be achieved through channel length scaling by reducing the physical dimensions and gate capacitance of the FETs. Owing to its one-dimensional (1D) ultrathin nature, electrostatic gate control of a carbon nanotube (CNT) is more efficient than that of a 3D Si channel, which allows for more aggressive channel length scaling in CNT field-effect transistors (CNTFETs). Moreover, CNTs are well known for their high mobility and saturation velocity.1 All of these exceptional properties make CNTs an ideal channel material and bring the promise of new generations of smaller and faster FETs for high-performance logic computing. Besides electrostatic gate control, device designs of contacts, gate stack, and layout will also impact the switching speed of the FET. For high mobility channel materials such as CNTs, designing the right gate stack and making good contacts are crucial to access their intrinsic material properties. The most common layout for a CNTFET is the Schottky barrier (SB) transistor,2 in which metal source/drain electrodes
are attached to an intrinsic CNT channel without complicated doping profiles. The contact interface and gate dielectric deposition are found to be critical to the SB-CNTFET device performance. In the following sections, we present an overview of research on CNT growth, a design paradigm for material imperfection tolerance, post-synthesis material preparation, CNT device fabrication and transport, a compact modeling and performance benchmark, p, n-FETs for CMOS logic, and the largest CNT integration up to date—a CNT computer— as well as 3D integration.
CNT array growth and imperfection-immune paradigm Controlled manufacturing of CNTs with desired diameter and chirality at predefined spots on a wafer remains one of the biggest challenges for CNT implementation in highperformance logic. While a CNTFET can be fabricated from a single CNT,3 this device design is perhaps not the most realistic basis for future high-performance integrated circuits (ICs). Even though a single CNT allows for extremely high current density, the current output of such a single-CNT device remains low due to the small size of the channel. Also, the
Zhihong Chen, Birck Nanotechnology Center, School of Electrical and Computer Engineering, Purdue University, USA; [email protected] H.-S. Philip Wong, Stanford University, USA; [email protected] Subhasish Mitra, Stanford University, USA; [email protected] Ageeth Bol, Eindhoven University of Technology, The Netherlands; [email protected] Lianmao Peng, Key Laboratory for the Physics and Chemistry of Nanodevices and Department of Electronics, Peking University, China; [email protected] Gage Hills, Stanford University, USA; [email protected] Nick Thissen, Department of Applied Physics, Eindhoven University of Technology, The Netherlands; [email protected]
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