Carrier Pocket Engineering for the Design of Low Dimensional Thermoelectrics with High Z 3D T
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Carrier Pocket Engineering for the Design of Low Dimensional Thermoelectrics with High Z3DT Takaaki Kogaa, Stephen B. Croninb, and Mildred S. Dresselhausb,c a Division of Engineering and Applied Sciences, Harvard University, Cambridge, MA 02138 b Department of Physics and cDepartment of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139
ABSTRACT The concept of carrier pocket engineering applied to Si/Ge superlattices is tested experimentally. A set of strain-symmetrized Si(20Å)/Ge(20Å) superlattice samples were grown by MBE and the Seebeck coefficient S, electrical conductivity σ, and Hall coefficient were measured in the temperature range between 4K and 400K for these samples. The experimental results are in good agreement with the carrier pocket engineering model for temperatures below 300K. The thermoelectric figure of merit for the entire superlattice, Z3DT, is estimated from the measured S and σ, and using an estimated value for the thermal conductivity of the superlattice. Based on the measurements of these homogeneously doped samples and on model calculations, including the detailed scattering mechanisms of the samples, projections are made for δ-doped and modulation-doped samples [(001) oriented Si(20Å)/Ge(20Å) superlattices] to yield Z3DT ≈ 0.49 at 300K. INTRODUCTION Early work on low dimensional thermoelectricity used simple theoretical models, such as for an isolated 1D and 2D electron gas [1], and the results of these calculations predicted a significant enhancement in the thermoelectric figure of merit ZT within the quantum well. The earliest attempts to show this enhancement experimentally were performed on 2D superlattices grown by molecular beam epitaxy (MBE) and their transport properties were measured [2, 3]. In these early samples, the barrier layer was made much thicker than the quantum well thickness, ensuring good quantum confinement of carriers in the quantum well. In these samples it was shown that the thermoelectric power factor, S2σ, of the quantum wells alone, neglecting the contribution from the barrier layers, was indeed enhanced. These experiments helped prove the principle, predicted theoretically, that thermoelectricity could be enhanced in low dimensional systems. In terms of a practical device, thick barrier layers provide a parasitic thermal conduction path, and result in a much degraded ZT for the entire sample. In the present work, we concern ourselves only with increasing Z3DT, which includes contributions from both the quantum wells and the barrier layers, that is the entire thermoelectric device. The systematic process by which low dimensional superlattices of given constituents are designed to optimize their 3D thermoelectric properties has been called “carrier pocket engineering”[4-7]. Within this framework, the large barrier widths that were used in previous proof-of-principle studies are
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