Characterization of Ultrathin Strained-Si Channel Layers of n-MOSFETs Using Transmission Electron Microscopy
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Characterization of Ultrathin Strained-Si Channel Layers of n-MOSFETs Using Transmission Electron Microscopy Dalaver H. Anjum1,3, Jian Li1, Guangrui Xia2, Judy L. Hoyt2, and Robert Hull1 1 Department of Materials Science & Engineering, University of Virginia, 116 Engineer’s Way, Charlottesville, VA 22904 2 Microsystems Technology Laboratories, Department of Electrical Engineering & Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139 3 Present Address: The Burnham Institute, 10901 North Torrey Pines Road, La Jolla, CA 92037 ABSTRACT Strained-Si based Field Effect Transistors (FETs) have enabled improvement of carrier transport in Metal Oxide Semiconductor (MOS)-based devices, both in the ON state of the device and in the sub-threshold region. This leads to devices with higher ratios of on-to-off current, improvements in the device sub-threshold slope, lower voltage operation, and carrier mobility enhancement. However, in order to understand the fundamental physics of these devices, it is important to address the stress conditions of the strained-Si channel layers after device processing, particularly after the ion-implantation process. In this work, we have studied Si+ self ion-implantation and thermally annealed strained-Si channel layers in n-MOSFETs. It has been observed that the density of defects in the strained-Si layer depends upon implant dose as well as thermal treatment. Using energy dispersive spectroscopy (EDS) spectra, it is found that Ge is present in the strained Si layer when analyzed after Si+ implantation and rapid thermal annealing. The presence of Ge in the strained Si channel layer causes relaxation of strain. This is verified by Convergent Beam Electron Diffraction (CBED) by measuring the lattice constant of the strained channel. It is concluded that electron mobility enhancements can be degraded in nMOSFETs due to presence of both Ge up-diffusion and defects. INTRODUCTION Ion implantation and the subsequent thermal treatment are key to the fabrication of strained channel MOSFETs. Ion implantation is thought to be the primary reason responsible for the production of defects that ultimately result in strain relaxation and transient enhanced diffusion (TED) of the dopants during subsequent thermal treatments. Different analysis techniques, such as transmission electron microscopy (TEM) and micro-Raman Laser Spectroscopy can be utilized to characterize the strains and stresses in the ion-implanted strained semiconductor layers.1 TEM is one of the most important analysis techniques because it allows one to determine strain and the nature of defects simultaneously, and at high spatial resolution. A significant difference between strained channel MOSFETs and conventional MOSFETs is the effects of high temperatures used during processing, e.g. during gate oxidation and implant annealing. High temperatures can degrade material properties through strain relaxation in the form of threading dislocations from the underlying relaxed buffer layer (see Figure 1) in strained MOS
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