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Charges and Dipoles at Semiconductor Interfaces Raymond T. Tung Research Center for Quantum Effect Electronics Tokyo Institute of Technology 2-12-1 O-okayama, Meguro-ku Tokyo, JAPAN 152-8552 ABSTRACT The formation of the Schottky barrier height at metal-semiconductor interfaces has often been discussed in terms of interface states. This paper examines theoretical models that specifically relate defects and other interface states (such as MIGS) to the interface dipole. These models usually rely on the assumption, which is also invoked in most experimental determination of interface state distribution, that the interface dipole can be broken up into the product of an interface charge and an interface distance/width. Various inconsistencies associated with this assumption are discussed, suggesting that the formation of the interface dipole is an integral process which cannot be divided. It is shown that the inclusion of the bond polarization at semiconductor interfaces, proposed in recent work, gives quantitative account of experimental Fermi level pinning effect. In addition, the bond polarization concept can be extended to the theoretical description of band offsets at epitaxial semiconductor heterojunctions. These results underscore the importance of correctly handling the chemistry at semiconductor interfaces in order to understand their electronic properties. SCHOTTKY BARRIER HEIGHT AND INTERFACE GAP STATES The Schottky-Mott condition, that the SBH, Φ oB, n , between a metal with a work function of

φ M and a semiconductor with an electron affinity of χ S is given by Φ oB ,n = φ M − χ S

(1)

follows directly from the requirement of the continuity of electrostatic potential and is obeyed in the absence of interface charge rearrangement. Experimentally, however, the SBH for common semiconductors is found to have only a weak dependence on the metal work function. This phenomenon, manifested by an interface behavior parameter S Φ ( ≡ ∂Φ oB ,n / ∂φ M ) of much less than 1, is known as “Fermi level (FL) pinning”.[1] Because of the poignancy of the FL pinning phenomenon, with S Φ < 0.2 for Si and GaAs, explanation of this effect alone had occupied the attention of almost all early SBH studies. Typically, surface states [2] due to broken bonds, deep-level defect states[3-5] of the semiconductor, and intrinsic metal-induced gap states (MIGS)[6-9] are envisioned to be present at the MS interface and they are assumed to pin the FL position of the semiconductor interface much like the way gap states are known to pin the FL position at the free surfaces of semiconductors. At the surface of a semiconductor, the net charge of the surface states exactly balances the (usually small) space charge in the depletion region. Therefore, the surface Fermi level is “pinned” near the charge neutrality level (CNL) of the F12.1.1 Downloaded from https://www.cambridge.org/core. Teachers College Library - Columbia University, on 09 Apr 2019 at 14:37:03, subject to the Cambridge Core terms of use, available at https://www.cambridge.org/core/te