Complete Symbolic Simulation of SystemC Models Efficient Formal Veri
In his master thesis, Vladimir Herdt presents a novel approach, called complete symbolic simulation, for a more efficient verification of much larger (non-terminating) SystemC programs. The approach combines symbolic simulation with stateful model checkin
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Vladimir Herdt
Complete Symbolic Simulation of SystemC Models Efficient Formal Verification of Finite Non-Terminating Programs With a Preface by Prof. Dr. Rolf Drechsler
Vladimir Herdt Bremen, Germany
BestMasters ISBN 978-3-658-12679-7 ISBN 978-3-658-12680-3 (eBook) DOI 10.1007/978-3-658-12680-3 Library of Congress Control Number: 2016930259 Springer Vieweg © Springer Fachmedien Wiesbaden 2016 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, speci¿cally the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on micro¿lms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a speci¿c statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper Springer Vieweg is a brand of Springer Fachmedien Wiesbaden Springer Fachmedien Wiesbaden is part of Springer Science+Business Media (www.springer.com)
Preface Electronic systems consist of a large number of interacting hardware- and software components. Only the hardware often is assembled of more than a billion transistors. To cope with this increasing complexity system description languages, which allow modeling at high level of abstraction, have been introduced and are focus of current research. They facilitate architectural exploration as well as Hardware/Software Co-Design. SystemC has become the de-facto standard for modeling at the system level. The SystemC model serves as reference for subsequent development steps. Errors in a SystemC model are very critical, since they will propagate and become very costly. Thus, developing verification methods for SystemC is of very high importance. Existing formal verification approaches at lower abstraction levels are already very sophisticated and require a profound technical understanding to
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