Conversion of Basal Plane Dislocations to Threading Edge Dislocations by High Temperature Annealing of 4H-SiC Epilayers
- PDF / 11,181,769 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 67 Downloads / 272 Views
Conversion of Basal Plane Dislocations to Threading Edge Dislocations by High Temperature Annealing of 4H-SiC Epilayers Xuan Zhang1 and Hidekazu Tsuchida1 1 Central Research Institute of Electric Power Industry, 2-6-1 Nagasaka, Yokosuka, Kanagawa 240-0196, Japan
ABSTRACT Conversion of basal plane dislocations (BPDs) to threading edge dislocations (TEDs) has been observed in 4H-SiC epilayers by simple high temperature annealing. Grazing incidence reflection synchrotron X-ray topography was used to image the dislocations in the epilayers. By comparing the X-ray topographs before and after annealing, some of the BPDs were confirmed to convert to TEDs from the epilayer surface. The dislocation behaviors during annealing are explained and the mechanism of BPD conversion is discussed. It is argued that the conversion process is realized by constricted BPD segments cross-slipping to the prismatic plane driven by the image force and TED glide on its slip plane driven by the line tension. Certain kinetic processes may assist the formation of constrictions on the BPDs. INTRODUCTION Basal plane dislocations (BPDs) in 4H-SiC epilayers are a limiting factor of making SiC bipolar devices. Under forward bias, stacking faults expand from the BPDs and cause the voltage drops across the p-i-n diodes to increase over time [1]. One direct way to eliminate BPDs from the epilayers is to grow epilayers on on-axis substrates [2]. Another approach is to utilize the phenomenon of BPDs converting to threading edge dislocations (TEDs) during off-axis epitaxy [3]. The conversion mostly happens at the interface. Several processing steps have been proposed to enhance the conversion ratio, including patterning or etching the substrate surface [4-6] and adding growth interruptions [7,8]. While the growth/processing parameters are being tuned and optimized, physical understanding of the phenomenon has also been improved. This paper reports our discovery of converting BPDs to TEDs in 4H-SiC epilayers by simple thermal annealing at high temperatures. Observations on the dislocation behaviors during annealing will be explained and the mechanism of BPD conversion will be discussed. EXPERIMENT Commercial 3-inch 4H-SiC n-type conductive wafers with 8° off-cut towards [11-20] were cut into 4 quarters and used as substrates. The epilayers were grown on the Si-face of the substrates in a vertical hot-wall reactor at ~1550°C with no intentional doping [9]. The thicknesses of the epilayers were about 10 μm. Thermal annealing experiments were performed
in an induction heating annealer in argon ambient. Before annealing, some of the epi-wafers were coated with photoresists. Carbon caps were formed at 800°C to prevent surface roughening at high annealing temperatures [10]. Most epi-wafers were annealed at 1800°C for 5 minutes to 3.5 hours. One epi-wafer was annealed at 2000°C for 5 minutes. The ramp-up rates were 40100°C/min from 1500°C to the desired temperatures. The cooling rates were less than 60°C/min. Grazing incidence reflection synchrotron X-ray topogr
Data Loading...
