Crosstalk in Modern On-Chip Interconnects A FDTD Approach
The book provides accurate FDTD models for on-chip interconnects, covering most recent advancements in materials and design. Furthermore, depending on the geometry and physical configurations, different electrical equivalent models for CNT and GNR based i
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Brajesh Kumar Kaushik V. Ramesh Kumar Amalendu Patnaik
Crosstalk in Modern On-Chip Interconnects A FDTD Approach 123
SpringerBriefs in Applied Sciences and Technology
More information about this series at http://www.springer.com/series/8884
Brajesh Kumar Kaushik V. Ramesh Kumar Amalendu Patnaik •
Crosstalk in Modern On-Chip Interconnects A FDTD Approach
123
Brajesh Kumar Kaushik Department of Electronics and Communication Engineering Indian Institute of Technology Roorkee Roorkee, Uttarakhand India
Amalendu Patnaik Department of Electronics and Communication Engineering Indian Institute of Technology Roorkee Roorkee, Uttarakhand India
V. Ramesh Kumar Department of Electronics and Communication Engineering Indian Institute of Technology Roorkee Roorkee, Uttarakhand India
ISSN 2191-530X ISSN 2191-5318 (electronic) SpringerBriefs in Applied Sciences and Technology ISBN 978-981-10-0799-6 ISBN 978-981-10-0800-9 (eBook) DOI 10.1007/978-981-10-0800-9 Library of Congress Control Number: 2016934012 © The Author(s) 2016 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper This Springer imprint is published by Springer Nature The registered company is Springer Science+Business Media Singapore Pte Ltd.
Preface
Advancement in VLSI technology offers gigascale integrated circuits in a system on-chip. In such circuits, interconnects play a key role in determining circuit performance such as time delay and power consumption. At high operating frequencies, the closely packed interconnects produce transient crosstalk. The crosstalk noise strongly influences the signal propagation delay and also causes logic or functional failure. Therefore, it is desirable to accurately model the crosstalk effects in the on-chip interconnects. Over the years, several mathematical models have been proposed for the analysis of CMOS-gate-driven coupled interconnect lines. However, most of these crosstalk noise models consider the nonlinear CMOS driver as a linear resistor. This
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