Debugging at the Electronic System Level
Debugging becomes more and more the bottleneck to chip design productivity, especially while developing modern complex integrated circuits and systems at the Electronic System Level (ESL). Today, debugging is still an unsystematic and lengthy process. Her
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Frank Rogin • Rolf Drechsler
Debugging at the Electronic System Level
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Frank Rogin Fraunhofer - Institut f ü r Integrierte Schaltungen Institutsteil Entwurfsautomatisierung Zeunerstr. 38 01069 Dresden Germany [email protected]
Rolf Drechsler Universität Bremen AG Rechnerarchitektur Bibliothekstr. 1 28359 Bremen Germany [email protected]
ISBN 978-90-481-9254-0 e-ISBN 978-90-481-9255-7 DOI 10.1007/978-90-481-9255-7 Springer Dordrecht Heidelberg London New York Library of Congress Control Number: 2010929863 © Springer Science +Business Media B.V. 2010 No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Cover design: eStudio Calamar S.L. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Contents
List of Figures List of Tables Preface Acknowledgements 1.
INTRODUCTION 1 General Objective of the Book 2 Summary of Contributions 3 Book Outline
2.
ESL DESIGN AND VERIFICATION 1 ESL Design 1.1 ESL Design Flow 1.2 System Level Language SystemC 1.3 Transaction Level Modeling in SystemC 2 ESL Verification 2.1 Simulation 2.2 Formal Verification 2.3 Semi-Formal Verification 2.4 Verifying SystemC Models 2.4.1 Simulation in SystemC 2.4.2 Semi-Formal Verification in SystemC 2.4.3 Formal Verification in SystemC 3 Our Debugging Approach 3.1 Terms 3.2 General Debug Process 3.3 Hierarchy of Debugging Techniques
xi xv xvii xix 1 2 5 7 9 9 10 15 16 18 19 19 20 21 21 22 24 25 25 26 27 v
Debugging at the ESL
vi 3.4
SIMD Data Transfer Example
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3.
EARLY ERROR DETECTION 1 Deduction Techniques in a Nutshell 1.1 Preliminaries 1.2 Related Work 2 Static Analysis Framework 2.1 Requirements 2.2 General Architecture 2.3 Generic Framework Components 2.3.1 Generic Symbol Table 2.3.2 Generic Dataflow Analysis 2.3.3 Generic Structural Analysis 2.4 Configuration and Adaptation 2.4.1 Implementation of Analyses 2.4.2 Tailoring to the Analyzed Language 2.5 Approach Rating 2.5.1 General Benefits 2.5.2 General Limitations and Risks 2.5.3 Benefits of REGATTA 2.5.4 Limitations of REGATTA 3 SystemC Design Analysis System 3.1 Implementation Effort 3.2 Configuration and Adaption 3.3 Example Analysis Flow 4 Experimental Results 4.1 SIMD Data Transfer Example Continued 4.2 Industrial SystemC Verification Environment 5 Summary and Future Work
33 34 34 38 40 41 41 43 43 45 49 51 51 53 55 55 56 56 57 57 58 58 61 63 63 65 68
4.
HIGH-LEVEL DEBUGGING AND EXPLORATION 1 Observation Techniques in a Nutshell 1.1 Overview 1.1.1 Logging 1.1.2 Debugging 1.1.3 Visualization 1.2 Related Work 2 System-Level Debugging 2.1 Requirements 2.2 Methodology
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Contents
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vii 2.2.1 Debug Levels 2.2.2 Debug Flow 2.
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