Defect Engineering
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edge base, and to show how defect engineering has provided new frontiers in product design, processing, and performance. Single-Crystal Substrates for Integrated Circuits Mytît: Defects dégrade performance and fabrication yield. Silicon The term "substrate" is derived from planar process technology, the basis of integrated circuit fabrication. A silicon single-crystal wafer of high purity and perfection is subjected to a séquence of process steps (which today number near 500!) that imprint the material heterogeneitjes constituting the circuit éléments (currently about 108 per chip). Figure 1 depicts the évolution of defect engineering for silicon substrates. The focus of the 1960s was réduction of dislocation density. Process yield for discrète bipolar transistors was limited by emitter-collector short circuits. The "Cottrell atmosphère" of metallic, contaminant impurities that
WAFER PREPARATION 1960 s
* CRYSTAL GROWTH
[ZXD h—-f-i" • LOW DISLOCATION DENSITY 1970 s
* POINT DEFECT CONTROL
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* OXYGEN AND CARBON
• DISTRIBUTED DEFECTS
Figure 1. Silicon substrate engineering during the last three décades. The focus has evolvedfrom "élimination of defects" to "controlled introduction of defects."
collected at the dislocation provided a filamentary conductor which threaded through the emitter-base-collector junctions.1 Defect engineering efforts succeeded in the 1970s with an industry standard of dislocation-free substrates. At the same time, the économie impact of an increasing number of process steps for circuit fabrication required leveraging in the form of increased wafer area (more circuits per process step). Various unexpected defect problems appeared. In the purest floatzoned silicon (background concentration oxygen 30 /xm from the surface
MRS BULLETIN/DECEMBER1991
Defect Engineering
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Figure 2. Schematic diagram of the effects of impurities on the dislocation density in GaAs.'4 Afull range of phenomena are available to the defect engineer: electronic control of point defect solubility, nonstoichiometry, and solid solution hardening al high concentrations.
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Figure 3. Control of threading dislocation density in heterostructure materials Systems: (a) cohérent interface; (b) incohérent interface with idéal termination of misfit array without threading dislocations; (c) TEM micrograph of thread-free Ge0.3o Sio.?o loyer (from Référence 2 0 |
MRS BULLETIN/DECEMBER1991
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