Degradation Process in Pentacene-Based Organic Field-Effect Transistors Evaluated by Three-Terminal Capacitance-Voltage
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Degradation Process in Pentacene-Based Organic Field-Effect Transistors Evaluated by Three-Terminal Capacitance-Voltage Measurements Yuya Tanaka1,2, Kohei Yamamoto2, Yutaka Noguchi3 and Hisao Ishii1,2,4, 1 Center for Frontier Science, Chiba University, Chiba 263-8522, Japan. 2 Graduate School of Advanced Integration Science, Chiba University, Chiba 263-8522, Japan. 3 School of Science and Technology, Meiji University, Kawasaki 214-8571, Japan. 4 Molecular Chirality Research Center, Chiba University, Chiba 263-8522, Japan. ABSTRACT By taking advantage of three-terminal capacitance-voltage (TT-CV) measurement, we investigated a formation of trapped charge in pentacene(Pn)-based organic field-effect transistors (OFETs) during the bias stress measurement. The shift of the turn-on voltage in transfer curve correlated well with the increase of trapped charge estimated from TT-CV curves. Moreover, TT-CV measurement revealed that the trapped charges were distributed inhomogeneously at the vicinity of the pentacene/insulator interface, indicating that the current does not obviously affect their formation. Thus we suggested that the trapped charges are formed by keeping Pn molecules as unstable cation (hole state) by the prolonged bias stress. INTRODUCTION Organic field-effect transistors (OFETs) are promising device because of their favorable features such as light-weight, flexibility, and low-cost fabrication [1-3]. Since OFETs were invented in 1980s [4-6], much efforts have been devoted to improve its performance through an application of feasible materials to organic and insulator layers, and an insertion of buffer layer at organic/insulator interface [7-9]. Consequently, the mobility of OFETs has increased drastically, however, the degradation mechanism still has not been fully clarified [10, 11]. In order to realize the practical use of OFETs, a deep understanding of its mechanism is needed. There are several kinds of performance variation due to the prolonged bias stress, such as a shift of the threshold voltage, an increase in the sub-threshold slope, a reduction of the fieldeffect mobility, an increase of the OFF current, and/or increased hysteresis of the transfer characteristics [10]. Among them, the threshold voltage shift is found with considerable frequency, which is caused by trapping of charge carriers in localized states. Thus, it is quite important to evaluate the detailed property of trapped charge in the device. The amount of trapped charges (Q trap ) is often estimated from the shifts of the threshold or turn-on voltages (V on ) [12, 13]. This analysis is based on the assumption that the trapped charges are uniformly distributed in the device. This is a valid argument if the trapped charges are formed by the current, however, Ryu et al. suggest that the current is not the cause of the bias stress effect based on the analysis of the drain voltage (V DS ) dependence of the threshold shift [14]. Capacitance-voltage (CV) measurements, such as impedance spectroscopy (IS) [15-17] and displacement current measur
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