Design and implementation of multiplication algorithm in quantum-dot cellular automata with energy dissipation analysis
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Design and implementation of multiplication algorithm in quantum‑dot cellular automata with energy dissipation analysis Hamed Kamrani1 · Saeed Rasouli Heikalabad1 Accepted: 20 October 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract QCA is an emerging nanotechnology for the design of digital system circuits based on electron interactions. QCA is used to design nanoscale circuits. Multiplier algorithms play an important role in computer computing, and algorithms with better performance speeds are more considerable. Booth multiplication algorithm is one of the multiplication algorithms that increases the multiplication speed by decreasing the number of partial products and using a smaller adder. In this paper, the Booth multiplication algorithm is designed and implemented in QCA. It has been tried to contain minimum number of cells and the least complexity and energy dissipation in the proposed design. Keywords QCA (quantum-dot cellular automata) · Nanotechnology · Booth multiplication algorithm · Adder
1 Introduction The role of multiplier algorithms in doing computer calculations is undeniable. The multiplier algorithms that have high speed and low power consumption and require lesser space for implementation are more considerable. The usual way to do binary multiplication is add/shift, in a way that the partial products are calculated firstly and then the partial products added by adders. The main standard for measuring the multiplier algorithms is the number of partial products. One of the best algorithms for reducing the number of partial products is Booth multiplication algorithms. This algorithm reduces the number of partial products by changing the number radix and thereby will improve the multiplication speed [1]. Latency is important in processing operations [2]. * Saeed Rasouli Heikalabad [email protected] 1
Department of Computer Engineering, Tabriz Branch, Islamic Azad University, Tabriz, Iran
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H. Kamrani, S. R. Heikalabad
So far, various designs of this algorithm have been performed by MOS or on FPGA [3, 4]. MOSFET has limitations in terms of circuit size and leakage current that QCA can overcome by using a new binary value transfer method [5]. In addition, the QCA operating frequency is very high. This feature draws a lot of attention in the design of circuits such as multipliers in which high performance speed is a key feature. Because the Booth multiplier has a complex structure consisting of several different digital elements, how to design and arrange these elements is also a major challenge in this technology. In this paper, it has been tried to propose a minimal and optimal design of the Booth multiplication algorithm in QCA by using capabilities that are hidden in QCA technology. In terms of logic design, we use three-input and five-input majority voting gates to implement the Booth multiplication algorithm in QCA. All the required digital elements are designed by these gates, the operation of which is described below. The re
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