Design and optimization of junctionless-based devices with noise reduction for ultra-high frequency applications
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Design and optimization of junctionless‑based devices with noise reduction for ultra‑high frequency applications Krishan Kumar1 · Ashish Raman1 · Balwinder Raj1 · Sarabdeep Singh1 · Naveen Kumar1 Received: 30 August 2020 / Accepted: 18 October 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract This paper offers the study of the noise performance of four devices namely junctionless dual-gate FET (JL-DGFET), junctionless nanowire FET (JL-NWFET), charge-plasma based dopingless dual-gate FET (DL-DGFET) and dopingless nanowire FET (DL-NWFET). This work examines the maximum Noise-Figure (NFmax.), Auto-correlation factor ()/ (), cross-correlation factor (), and output impedance (real Zo). To understand the performance of devices, analog characteristics of all four devices and effect on these characteristics with the variations of different device structure parameters are analyzed and compared. Internal physics of device is understood by device design parameters such as electric field, channel potential, carrier mobility and carrier concentration. It is observed from the simulated results that JL-DGFET has better noise performance, highest ION/IOFF current ratio than other devices. Keywords Junctionless · Dual-gate · Charge-plasma · Dopingless
1 Introduction As compared to conventional junction based FETs, Junctionless (JL) FETs have no junction between the source/drain and channel [1, 2]. Junctionless based devices (FET/TFET) solve the process challenges such as low thermal budget and large doping concentration gradients [3–5]. Because of working under volume conduction mode, JL FETs improve carrier transit speed and minimize surface roughness scattering [3]. However, due to higher doping concentration (> 1019 cm−3) it has some challenges such as threshold voltage variability due to random doping fluctuations (RDFs), poor switch off capability [6] and the requirement of a higher gate work function to turn off the device. To overcome these problems, dopingless FETs based on charge-plasma concept are used where source and drain are formed by charge plasma concept [5]. The implementation of charge-plasma concept requires a few stringent conditions. Metals with specific work functions are deposited onto the source/drain region with an oxide layer to induce the desired charge carriers [7]. With recent fabrication technologies, it is possible
to tune the device performance with the help of nanomaterials [8–10]. Recently p–n junction diode [11], dopingless BJT [12] and TFET [13, 14] has used the concept of charge plasma. Similarly, MOSFETs [15, 16] is also explored by this concept. As compared to dual-gate FETs such as JLDGFET and DL-DGFET, gate-all-around (GAA) silicon nanowire FETs such as JL-NWFET and DL-NWFET provides the best electrostatic control, higher packaging density, and short channel effects (SCEs) immunity [17–19]. For better device scaling, a nanowire with gate-all-around structure is used [20–22]. The remainder of the paper is structured as follows. In Sect. 2, the device structure
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