Design and validation of an artificial neural network based on analog circuits
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Design and validation of an artificial neural network based on analog circuits Fikret Bas¸ar Gencer1 • Xhesila Xhafa1 • Benan Beril ˙Inam1 • Mustafa Berke Yelten1 Received: 7 March 2020 / Revised: 7 March 2020 / Accepted: 5 September 2020 Ó Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract This paper focuses on the design and validation of an analog artificial neural network. Basic building blocks of the analog ANN have been constructed in UMC 90 nm device technology. Performance metrics of the building blocks have been demonstrated through circuit simulations. The weights of the ANN have been estimated through an automated backpropagation algorithm, which is running circuit simulations during weight optimization. Two case studies, the operation an XOR logic gate and a full adder circuit have been captured using the proposed analog ANN. Monte Carlo analysis of the XOR gate reveals that the analog ANN operates with an accuracy of 99.85%. Keywords Artificial neural networks Analog circuits XOR gate Full adder
1 Introduction Artificial neural networks (ANNs) have originated by the effort to mimic the operation of a neuron. This has led to the generation of smart systems capable of learning from the available input–output samples of a system [3]. Through supervised learning in ANNs, multiple complex problems in various disciplines regarding optimization, classification, pattern recognition, and data fitting become easier to solve [11, 18, 23]. ANNs are mostly implemented in software based on the extensive capabilities of modern computing. Nevertheless, in many applications, problems regarding the computational complexity arise during implementation [8]. The structure of a typical ANN suggests that its operation can be greatly optimized when parallel processing can be adopted, which is also applicable when the ANN is implemented in hardware [4, 20, 22]. There have been analog, digital, and mixed-signal implementations of ANNs in the literature [15]. Among these approaches, analog implementations offer compliance with the continuous nature of ANNs, and they can be employed in sensor & Mustafa Berke Yelten [email protected] 1
implementations, which enable analog signal processing without the need for analog-to-digital converters. The noise and the nonlinearity introduced by the analog circuits can be tolerated by the back-propagation (BP) that allows ANNs to operate correctly in the presence of computational errors [13]. Furthermore, analog circuits can be designed to be of low power and smaller area. This can potentially lead to energy-efficient implementations of analog neurons in comparison to digital neurons [16, 18, 25]. An analog ANN performs multiplication, subtraction, and summation along with the activation function evaluation. In our previous work, we developed the analog blocks of these basic operations and demonstrated the functionality of an analog ANN in UMC 90 nm CMOS technology [9]. In this paper, we extend the validation of our analog ANN on a full-adder. We also provid
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