Design of a Transparent Pipeline Based on Synchronous Elastic Circuits
This chapter presents a transparent pipeline architecture based on the synchronous elastic circuits. Compared with a traditional synchronous pipeline, a transparent pipeline can reduce dynamic clock power dissipation by reducing the amount of clock pulses
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Abstract This chapter presents a transparent pipeline architecture based on the synchronous elastic circuits. Compared with a traditional synchronous pipeline, a transparent pipeline can reduce dynamic clock power dissipation by reducing the amount of clock pulses required for data latching. Moreover, with the help of the synchronous elastic properties, our design can also provide tolerance to variations in computation and communication delays. The proposed architecture has been implemented by the Verilog HDL and synthesized with Altera Quartus II. The experimental results performed on a five-stage pipeline have also shown the power efficiency of our architecture. Keywords Elastic • Pipeline • Transparent
1 Introduction In modern VLSI design, clock power plays an important role in chip power dissipation. Clock gating is an efficient technique widely used in low-power designs [1, 2]. Transparent pipelining is also a clock-gating solution for reducing dynamic power dissipation by reducing the amount of clock pulses that are redundant to the correct operation of a pipelined design [3–5]. In a traditional pipeline, the latches of a pipeline are assumed to be opaque by default to avoid data races between pipeline stages. But in a transparent pipeline, the internal latches are kept transparent by default to allow data items that are sufficiently separated to propagate through the pipeline without generating any clock pulses. Such separation often occurs in pipeline stalls of instruction execution caused by data dependencies. Since data
R.-D. Chen (*) • S.-H. Chang Department of Computer Science and Information Engineering, National Changhua University of Education, Changhua 500, Taiwan, R.O.C. e-mail: [email protected] J. Juang and Y.-C. Huang (eds.), Intelligent Technologies and Engineering Systems, Lecture Notes in Electrical Engineering 234, DOI 10.1007/978-1-4614-6747-2_73, # Springer Science+Business Media New York 2013
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races between latch stages can be avoided by properly separating data items in a transparent pipeline, a transparent latch needs to be clocked only when a true data race occurs. The number of required clock pulses can then be reduced by proper control of the gated clock signals. Therefore, the clock power can be significantly reduced by relaxing the clocking requirements of the latches in a pipeline. Synchronous elastic circuits are a form of discretized asynchronous circuits [6–8]. The elastic property makes it possible to tolerate unpredictable timing variations in the computations and communications of a circuit and its environment. By this synchronous elasticity, there is no need to fix the communication delays as used in traditional designs. The implementation of elastic circuits relies on the clock-based synchronous handshake protocol to control the latching of data items. The handshake signals are based on valid and stall signals, and to achieve elasticity, no specific assumption is made about the implementation of the circuit. This chapter incorpo
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