Design of Low-Cost FPGA Hardware for Real-time ICA-Based Blind Source Separation Algorithm
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Design of Low-Cost FPGA Hardware for Real-time ICA-Based Blind Source Separation Algorithm Charayaphan Charoensak School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798 Email: [email protected]
Farook Sattar School of Electrical and Electronic Engineering, Nanyang Technological University, Nanyang Avenue, Singapore 639798 Email: [email protected] Received 29 April 2004; Revised 7 January 2005 Blind source separation (BSS) of independent sources from their convolutive mixtures is a problem in many real-world multisensor applications. In this paper, we propose and implement an efficient FPGA hardware architecture for the realization of a real-time BSS. The architecture can be implemented using a low-cost FPGA (field programmable gate array). The architecture offers a good balance between hardware requirement (gate count and minimal clock speed) and separation performance. The FPGA design implements the modified Torkkola’s BSS algorithm for audio signals based on ICA (independent component analysis) technique. Here, the separation is performed by implementing noncausal filters, instead of the typical causal filters, within the feedback network. This reduces the required length of the unmixing filters as well as provides better separation and faster convergence. Description of the hardware as well as discussion of some issues regarding the practical hardware realization are presented. Results of various FPGA simulations as well as real-time testing of the final hardware design in real environment are given. Keywords and phrases: ICA, BSS, codesign, FPGA.
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INTRODUCTION
Blind signal separation, or BSS, refers to performing inverse channel estimation despite having no knowledge about the true channel (or mixing filter) [1, 2, 3, 4, 5]. BSS technique has been found to be very useful in many real-world multisensor applications such as blind equalization, fetal ECG detection, and hearing aid. BSS method based on ICA technique has been found effective and thus commonly used [6, 7]. A limitation using ICA technique is the need for long unmixing filters in order to estimate inverse channels [1]. Here, we propose the use of noncausal filters [6] to shorten the filter length. In addition to that, using noncausal filters in the feedback network allows a good separation even in the case where the direct channels filters do not have stable inverses. A variable step-size parameter for adaptation of the learning process is introduced here to provide a fast and stable convergence. FPGA architecture allows optimal parallelism needed to handle the high computation load of BSS algorithm in real This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
time. Being fully custom-programmable, FPGA offers rapid hardware prototyping of DSP algorithms. The recent advances in IC processing technology and innovations in the archi
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