Device simulations of a novel nanostructured CdS/CdTe solar cell with back contacts
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Device simulations of a novel nanostructured CdS/CdTe solar cell with back contacts Dinesh Kumar1 · N. Shyam Krishnan1 · Murugaiya Sridar Ilango2 · Sheela K. Ramasesha3 Received: 17 June 2019 / Accepted: 18 October 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Device simulations of a novel nanopillar-based n-CdS/p-CdTe solar cell with back contacts are carried out using the SILVACO technology computer-aided design (TCAD) device simulator. The device consists of nanopillars of CdTe coated with a very thin layer of CdS. It is shown that, for nanopillars with increasing height but given width as well as increasing width and given height, device performance parameters such as the open-circuit voltage (Voc), short-circuit current density (Jsc), fill factor, and solar cell conversion efficiency (η) increase. However, there is an optimum number of nanopillars that can be integrated into a given device area, while integration of more or fewer than this optimum value will deteriorate the device performance. Keywords CdS/CdTe solar cell · Nanopillar · Back contact · Photovoltaic (PV) devices · TCAD simulation
1 Introduction To harness and achieve the expected breakthrough in photovoltaic technology, continuous efforts have been made to boost the conversion efficiency of solar cells at a lower production cost. Extensive progress has been made in this regard by understanding and fabricating a wide range of nanowall/ nanopillar-based solar cells with the aim of enhancing the performance by modifying the device structure [1], different materials [2], using different electrode materials [2–8], and effectively harvesting light via trapping and scattering [9]. Currently, CdTe/CdS-based solar cells are the most promising thin-film technology, owing to their numerous beneficial properties towards the achievement of cost-effective high-efficiency solar cells [10]. Aligned nanostructure arrays have been regarded as an ideal architecture for photovoltaic applications because they provide a direct pathway for charge transport as well as a high junction area [11]. * Dinesh Kumar [email protected] 1
Department of Physics, JAIN (Deemed-to-be-University), Bengaluru, India
2
Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science, Bengaluru, India
3
National Institute of Advanced Studies, Indian Institute of Science Campus, Bengaluru, India
All device designs/structures proposed to date have shown improvements in parameters of interest such as the shortcircuit current density (Jsc), open-circuit voltage (Voc), fill factor (FF), solar cell conversion efficiency (η), quantum efficiency, and spectral response. A considerable number of research papers have been published in this context to date, where both contacts have been realized on the same plane at the back side of the device. An array of CdS/CdSe core/shell nanowalls [9, 10] and a stacked nanowire window-absorbertype solar cell structure [10–12] have been proposed, resulting in moderate enhancement of the
