Digital Logic Design Using Verilog Coding and RTL Synthesis
This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of
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Digital Logic Design Using Verilog Coding and RTL Synthesis
Digital Logic Design Using Verilog
Vaibbhav Taraate
Digital Logic Design Using Verilog Coding and RTL Synthesis
123
Vaibbhav Taraate Semiconductor Training @ Rs.1 Pune, Maharashtra India
ISBN 978-81-322-2789-2 DOI 10.1007/978-81-322-2791-5
ISBN 978-81-322-2791-5
(eBook)
Library of Congress Control Number: 2016936278 © Springer India 2016 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper This Springer imprint is published by Springer Nature The registered company is Springer (India) Pvt. Ltd.
Dedicated To the Supreme Lord of Intelligence And To All Students and Readers!
Preface
Today’s century is era of miniaturization and high-speed chips, and complex ASICs are designed in lesser time as compared to before. The technology evolution from 1990 has opened up a new paradigm for ASIC designers. Customers are always expecting the speedy delivery of the ASIC products and it always accumulates the good amount of pressure to come up with the high-performance design using less number of resources. The evolution in the process node technology in the past decade has started the real evolution in the semiconductor industry! Many new design techniques and flows got evolved and stabilized in the past decade. Many EDA tool companies help designers to complete the design in shorter time span. In today’s industrial scenario, designer doesn’t spend more time to draw the schematic to design the digital logic circuits. The EDA tools have enabled the best design practices by using hardware description languages such as VHDL and Verilog. The synthesis tools are used primarily to convert the HDL into the equivalent logic structure or gate level netlist. The latest EDA tool features have also improved the productivity and efficiency of the design team! The book is organized into three sections; the first section consists of Chaps. 1–9 and describes about the digital logic design and synthesizable Verilog
