Directed block copolymer self-assembly for nanoelectronics fabrication
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This paper provides an overview of directed self-assembly (DSA) options that exhibit potential for enabling extensible high-volume patterning of nanoelectronics devices. It describes the current set of research requirements, which a DSA technology must satisfy to warrant insertion consideration, and summarizes the state-of-the art. The primary focus is on chemical patterning and graphoepitaxial approaches to directing block copolymer (BCP) based assembly. These options exhibit the nearest-term potential, among the emerging DSA technologies, for satisfying projected International Technology Roadmap for Semiconductors (ITRS) patterning requirements. The paper concludes with a selected set of additional challenges, which represent potential barriers to the integration of directed BCP patterning into a nanoelectronics manufacturing line, as well as a few emerging application opportunities for related functional materials. A glossary of acronyms and terms may be found at the end of this manuscript.
I. BACKGROUND A. Justification
With the continued exponential growth of fabrication facility and exposure tool costs,1–3 the current nanoelectronics fabrication paradigm may not be sustainable.4,5 By 2004, the semiconductor lithographic community perceived a rapidly approaching “red brick wall” that has been called the lithographic “triangle of death.” This term refers to the apparent trade-off in conventional topdown lithography between three critical and interdependent chemically amplified resist performance factors, i. e., resolution, throughput, and line edge roughness. The Z-parameter is one of several useful metrics for quantifying the trade-offs among LER, resolution, and dose,6–10 as it appears to be relatively constant for a given exposure tool and illumination system. Z is defined, such that: Z ½Exposure tool; Illumination 5 ðhalf -pitchÞ3 LER2 sensitivity In 2007, various patterning options, such as: double exposure, double patterning, and spacer double patterning6; lithography-friendly design rules; and model-based OPC corrections were projected to be necessary techniques to achieve the projected CD and dimensional variability requirements at and beyond the 32 nm dynamic random access memory (DRAM) ½ pitch technology node
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Address all correspondence to this author. e-mail: [email protected] DOI: 10.1557/jmr.2010.74 122
J. Mater. Res., Vol. 26, No. 2, Jan 28, 2011
http://journals.cambridge.org
Downloaded: 11 Mar 2015
(2013).11 However, these techniques add significant complexity and cost to the lithographic process. They also make it more difficult to achieve the required overlay targets. At the same time, chemically amplified resists appeared to be approaching their respective resolution and dimensional control limits of ~30 nm half pitch, due to acid diffusion, and line width roughness limits of ~4.5 nm (3r).11 Today, the list of difficult lithography challenges continues to grow. In 2009, the International Technology Roadmap for Semiconductors (ITRS) Lithography International Technology Working Group (ITWG)
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