Dispersion Engineering of Three-Dimensional Silicon Photonic Crystals: Fabrication and Applications
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Dispersion Engineering of Three-Dimensional Silicon Photonic Crystals: Fabrication and Applications Sriram Venkataraman, Garrett Schneider, Janusz Murakowski, Shouyan Shi and Dennis W. Prather Electrical Engineering, University of Delaware, Newark, DE ABSTRACT In this paper, we propose the design and fabrication of buried silicon optical interconnect technology, the sub-surface silicon optical bus (S3B). The proposed approach relies on engineering the dispersion properties of embedded silicon three-dimensional photonic crystals to create sub-micron routing channels and control light propagation. Further, we present a method for the fabrication of buried three-dimensional (3D) photonic-crystal structures using conventional planar silicon micromachining. The method utilizes a single planar etch mask coupled with time-multiplexed, sidewall-passivating, deep anisotropic reactive-ion etching, to create an array of spherical voids with three-dimensional symmetry. Preliminary results are presented that demonstrate the feasibility of realizing chip-scale optical interconnects using our proposed approach. INTRODUCTION The 2003 International Technology Roadmap for Semiconductors highlights key interconnect challenges for next-generation microprocessors and computing systems. The roadmap suggests that the most difficult challenges in the near term include the rapid introduction of interconnect processes compatible with device roadmaps, coupled with fine dimensional control and providing good mechanical stability and thermal budget1. The continued push towards finer geometries, higher frequencies and larger chip sizes increasingly exposes the disparity between interconnect needs and projected interconnect performance. Further, the interconnect technologies should be able to meet performance requirements and manufacturing targets by leveraging low-cost conventional mass fabrication techniques and provide solutions to address global wiring scaling issues. The economies of scaling achieved by extending Moore’s Law have lead to the dominance of silicon in the microelectronics industry; conversely only modest progress in silicon-based optoelectronic circuits has been achieved in recent decades. However, recent progress towards a silicon light source by erbium doping2, nanostructures that enhance quantum effects3, novel approaches such as dislocation engineering4, optical amplification through Raman effect5 and free-carrier dispersion based optical modulation6, coupled with need for alternate mechanisms to solve the interconnect bottleneck, has renewed the interest in silicon microphotonics. One of the other major obstacles to the realization of silicon microphotonics is chip-scale optical interconnects7 due to incompatibility of optical device materials and disparate integration scales with electronic devices and ICs. In this paper, we propose a buried silicon optical interconnect technology, the sub-surface silicon optical bus (S3B) with the ability to meet the challenges cited earlier by the semiconductor roadmap, specific
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