Effect of Annealing on the Structural, Mechanical and Tribological Properties of Electroplated CU thin Films
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EFFECT OF ANNEALING ON THE STRUCTURAL, MECHANICAL AND TRIBOLOGICAL PROPERTIES OF ELECTROPLATED Cu THIN FILMS P. Shukla, A. K. Sikder, P.B. Zantye, Ashok Kumar, and M. Sanganaria Nanomaterials and Nanomanufacturing Research Center Department of Mechanical Engineering University of South Florida, 4202 East Fowler Avenue, Tampa, FL 33620 Novellus System, Inc., San Jose, CA 95134 ABSTRACT The increasing demand for faster and more reliable integrated circuits (ICs) has promoted the integration of Copper-based metallization. Electroplated Cu films demonstrate a microstructural transition at room temperature, known as self annealing. In this paper we intend to investigate the annealing behavior of electroplated Cu films grown on a seed Cu layer on top of the barrier layers over a single crystal silicon substrate. All the samples were undergone through a multistep annealing process. Grazing incident x-ray diffraction pattern shows stronger x-ray reflections from Cu (111) and (220) planes but weaker reflections from (200), (311) and (222) planes in all the electroplated Cu samples. Transmission electron microscopy was performed on the cross section of the samples and the diffraction pattern showed the crystalline behavior of both seed layer and electroplated Cu. Nanoindentation was performed on all the samples using the continuous stiffness measurement (CSM) technique and it was found that the elastic modulus varies from 110 to 130 GPa while the hardness varies from 1 to 1.6 GPa depending on the annealing conditions. The tribological properties of all the copper films were also measured using the Bench Top CMP tester. Subsequently, Nanoindentation was performed on the samples after polishing the top surface in order to investigate the work hardening and an increase in hardness and modulus was observed. Finite Element Modeling was performed in order to investigate the stress behavior during nanoindentation. INTRODUCTION The interconnect RC-delay (resistance-capacitance) has become dominant in determining overall device performance. The RC delay can be reduced by lowering the capacitance using low permittivity (low-k) materials as interlayer dielectrics (ILD) and by lowering the resistance using interconnect material with lower resistivity. Electroplated (EP) Cu has rapidly been adopted in deep submicron ULSI technology due to its lower resistivity and thus resulting in improved electromigration reliability [1–3]. Electroplated Cu films undergo a structural transition even at room temperature, which involves grain growth and texture changes [4,5] called as self-annealing process, which leads to a dramatic drop of the resistivity over time. The self-annealing for EP Cu films has become a constraint for reliability and reproducibility of Cu interconnect process, because changes of grain size and hardness have influence on electromigration and CMP process [6, 7]. For most reliability tests, knowledge of the thin film constitutive mechanical behavior is required. Mechanical properties of thin films often differ from those
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