Effect of Texture on Hillock Formation in Aluminum Films
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Effect of Texture on Hillock Formation in Aluminum Films
T. Muppidi, Y. Kusama and D.P. Field School of Mechanical and Materials Engineering, Washington State University Pullman, WA 99164-2920 USA
ABSTRACT Stress voiding describes a phenomenon in thin interconnect lines where hillocks and voids are formed during thermal cycling due to the stresses caused by the difference in the thermal expansion coefficients of metal used in the interconnect lines and the substrate material. The effect of texture on stress voiding in aluminum interconnects is investigated using orientation imaging microscopy (OIM©) and scanning electron microscopy. Aluminum films were deposited by PVD deposition onto sublayers of Ti and Ti plus TiN and were analyzed for crystallographic texture and grain boundary structure using OIM©. These films were later annealed at 400ºC for 1 hour and cooled. The specimens were examined for the presence of hillocks and voids using a scanning electron microscope. The results show strongly textured (111) films are more resistant to hillock and void formation.
INTRODUCTION Aluminum has been used as an interconnect material in integrated circuit manufacture for several decades. Currently, a representative aluminum line has a rectangular cross-section of submicron dimensions, and is subject to thermal expansion misfit, electric current and elevated temperature. The substantial forces acting in a small dimension have caused problems for IC manufactures and process designers since integrated circuits came into being. Integrated circuit fabrication involves thermal cycling processes such as deposition of the passivation layers. The difference in the thermal expansion coefficients of the metal and the substrate and surrounding materials develops high stresses in the interconnect lines. These stresses may be relaxed in many different ways, such as by dislocation glide/climb, void/hillock formation, and, in some cases, grain growth. Stress voiding has been identified as one of the principle mechanisms that cause failure of interconnects found in modern VLSI processes. The problem, which was first identified in 1984 by Klema et al. [1] and Curry et al. [2], is likely to become even more significant as integration levels increase (width of the cross-sectional area reduced below 1 µm and interconnects become longer). This failure is caused by the nucleation and growth of voids in the aluminium line under conditions of high stress at elevated temperatures. Though the exact mechanism for the formation of hillocks is not yet known, it is believed to occur by stress induced diffusion along the grain boundaries and other high energy interfaces in the material [3]. This process is not assisted by current
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flow in the metal line as is the case with electromigration, where the electro
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