Electrical Characteristics of TaO x N y /ZrSi x O y Stack Gate Dielectric for MOS Device Applications
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Electrical Characteristics of TaOxNy/ZrSixOy Stack Gate Dielectric for MOS Device Applications Hyungsuk Jung, Hyundoek Yang, Kiju Im, and Hyunsang Hwang* Department of Materials Science and Engineering Kwangju Institute of Science and Technology #1, Oryong-dong, Puk-gu, Kwangju, 500-712, KOREA Electronic mail: hwanghs@ kjist.ac.kr
ABSTRACT This letter describes a unique process for the preparation of high quality tantalum oxynitride (TaOxNy) with zirconium silicate (ZrSixOy) as an interfacial layer for use in gate dielectric applications. Compared with conventional native silicon oxide and oxynitride as an interfacial layer, tantalum oxynitride (TaOxNy) MOS capacitors using zirconium silicate (ZrSixOy) as an interfacial layer exhibit lower leakage current levels at the same equivalent oxide thickness. We were able to confirm TaOxNy/ZrSixOy stack structure by auger electron spectroscopy (AES) and transmission electron microscope (TEM) analysis. The estimated dielectric constant of TaOxNy and ZrSixOy were approximately 67 and 7, respectively. The zirconium silicate is a promising interfacial layer for future high-k gate dielectric applications. INTRODUCTION The scaling of gate dielectric thickness is the most difficult issue for the development of the next generation ULSI metal oxide semiconductor field effect transistor (MOSFET) devices. Considering the technology roadmap, an equivalent oxide thickness less than 15Å is necessary to meet the requirement of sub-100 nm MOSFET devices.1 Due to the low dielectric constant and high tunneling leakage current, the scaling of SiO2 below 20Å with acceptable leakage current levels is very difficult. To satisfy the requirements for sub-100 nm MOSFET devices, it is necessary to develop materials with excellent electrical characteristics including a dielectric constant higher than 40, interface state density less than 1x1011/cm2-eV, tunneling current lower than 10mA/cm2 under constant operating bias conditions and negligible hysterisis effect. Ta2O5 has been investigated in terms of MOS gate dielectric applications.2,3 Considering the 5~10Å-thick interfacial SiO2 layer which is necessary to minimize interface state density and the intermixing of silicon and Ta2O5, the dielectric constant of Ta2O5 is not sufficient to obtain an equivalent dielectric thickness of less than 20Å with acceptable leakage current level. Recently, K4.6.1
zirconium oxide and zirconium silicate have been investigated as alternatives to SiO2 gate dielectrics due to their excellent thermal stability with silicon substrates.4,5 It is also reported the dielectric constant of TaOxNy prepared by rapid thermal nitridation of Ta2O5 deposited on Ru layer is approximately 100.6 Recently, we reported excellent electrical characteristics of TaOxNy gate dielectric on silicon substrate prepared by nitridation and reoxidation of Ta2O5.7 Although the TaOxNy film exhibits dielectric constants higher than 60, the interfacial SiO2 is necessary to prevent intermixing and high interface state density problems. In this paper,
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