Electromigration Inside Logic Cells Modeling, Analyzing and Mitigati
This book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the
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tromigration Inside Logic Cells Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS
Electromigration Inside Logic Cells
Gracieli Posser • Sachin S. Sapatnekar Ricardo Reis
Electromigration Inside Logic Cells Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS
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Gracieli Posser Instituto de Informática - PPGC/PGMicro Universidade Federal do Rio Grande do Sul (UFRGS) Porto Alegre, Rio Grande do Sul, Brazil
Sachin S. Sapatnekar Department of Electrical and Computer Engineering University of Minnesota Minneapolis, MN, USA
Ricardo Reis Instituto de Informática - PPGC/PGMicro Universidade Federal do Rio Grande do Sul (UFRGS) Porto Alegre, Rio Grande do Sul, Brazil
ISBN 978-3-319-48898-1 DOI 10.1007/978-3-319-48899-8
ISBN 978-3-319-48899-8 (eBook)
Library of Congress Control Number: 2016959979 © Springer International Publishing AG 2017 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper This Springer imprint is published by Springer Nature The registered company is Springer International Publishing AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland
Preface
Electromigration (EM) in on-chip metal interconnects is a critical reliability-driven failure mechanism in nanometer-scale technologies. Usually, works in the literature that address EM are concerned with power network EM and cell to cell interconnection EM. This work deals with another aspect of the EM problem, the cell-internal EM. This work specifically addresses the problem of electromigration on signal interconnects and on Vdd and Vss rails within a standard cell. There are few studies in the literature addressing this problem, and the ones that can model EM are using a very simple model. To our best knowledge, this is the first work that analyzes, models, and reduces the EM effects on the signals inside cells by projecting the pin placement. In this work, cell-internal EM is modeled incorporating Joule heating effects
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