Enabling self-adaptability of small scale and large scale security systems using dynamic partial reconfiguration
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ORIGINAL RESEARCH
Enabling self‑adaptability of small scale and large scale security systems using dynamic partial reconfiguration B. C. Manjith1 · R. Dhanalakshmi2 Received: 9 May 2020 / Accepted: 28 October 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract The application areas of field programmable gate arrays (FPGAs) are increasing due to its hardware acceleration and reprogrammable features. From large-scale computation systems like cloud, aerospace, and defence to small-scale computation systems like home automation and mobile phones, the dynamic partial reconfiguration property is found to be attractive to design adaptive systems for self-reconfiguration and self-healing. The article presents two self- adaptive security systems for small scale as well as for large-scale systems. The security system is designed to include encryption accelerators and hash code generation accelerators. The security system designed for small-scale systems saves space and power using hardware adaptation by loading or creating only the required accelerator during execution of the application. It uses light weight cryptographic algorithms. A second design for large-scale systems focuses on getting more throughput by allocating more resources to the required accelerator at runtime. Two designs are created for hardware adaptation based on the accelerator requirement at runtime. Proposed adaptive design for small-scale systems achieved 68.50% decrease in resource consumption and design for large-scale systems achieved 25.93% more throughput than the best existing implementations. Keywords FPGA · Self-adaptive system · Partial reconfiguration · Security · Reconfigurable partition · Reconfigurable modules · PR controller
1 Introduction The extent to which the processor can be pushed to perform the ever increasing workload with same performance had a limit. Dedicated hardware for doing application specific computation came in the form of Application Specific Integrated Circuits (ASIC). ASIC was made to perform critical tasks and has highly optimized resources. The limitation of ASIC was found to be its flexibility. Since the circuit in ASIC is configured permanently, it has to be idle in places where its assigned job is currently not available. Field programmable gate arrays (FPGAs) introduced flexibility in hardware which the ASIC lacks. FPGAs could able to introduce the software flexibility to hardware performance. * B. C. Manjith [email protected] 1
Computer Science and Engineering Department, Indian Institute of Information Technology, Kottayam, Kerala, India
Computer Science and Engineering Department, Indian Institute of Information Technology, Tiruchirappalli, Tamil Nadu, India
2
FPGAs can be configured to perform one task and later on can be reconfigured to perform a different task if required. Reconfiguration can be a simple error correction in the circuit, change of a parameter according to the algorithm or change of the entire circuit with a new one to perform an entirely different ta
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