Engineered tantalum aluminate and hafnium aluminate ALD films for ultrathin dielectric films with improved electrical an
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Engineered tantalum aluminate and hafnium aluminate ALD films for ultrathin dielectric films with improved electrical and thermal properties Robert B. Clark-Phelps, Anuranjan Srivastava, Lance Cleveland, Thomas E. Seidel, and Ofer Sneh Genus, Inc. Sunnyvale, CA 94089 ABSTRACT Continued scaling of device dimensions requires deposition of high-quality thin films with a thickness of 50 angstroms or less. Nucleation effects in typical CVD processes make it difficult to achieve continuous films in this thickness regime. Atomic layer deposition (ALD), a technique developed over 25 years ago but applied to IC processing only recently, enables deposition of ultra-thin films with atomic-scale precision. This technique offers 100 percent step coverage of high aspect ratio features, as-deposited films which are amorphous and free of pinholes, excellent within-wafer uniformity and wafer-to-wafer uniformity, and favorable electrical properties. Moreover, ALD offers the opportunity to engineer material properties by creating layered structures (nanolaminates) and mixtures (alloys) which combine advantageous properties of different materials. These last features may be critical in efforts to replace silicon dioxide as the industry’s dielectric workhorse if no single material emerges as a suitable direct replacement. The nanolaminate capability of ALD will be discussed with physical and electrical data on nanolaminates of aluminum oxide with tantalum pentoxide and aluminum oxide with hafnium oxide. Individual nanolaminate layers can be varied from tens of angstroms to as little as 1-2 atomic layers. Data for Al2O3/Ta2O5 and Al2O3/HfO2 alloys will also be presented demonstrating the ability to create materials with controlled, variable composition. The alloy and nanolaminate capabilities enable the creation of graded interfaces and atomically smooth transitions between different materials. Prospects for application of these materials to gate stacks and capacitors will be assessed. INTRODUCTION As many researchers have documented, scaling requirements for CMOS technology are rapidly reaching fundamental physical limits as well as practical limits caused by variation in standard manufacturing processes. The 1999 International Technology Roadmap for Semiconductors calls for gate dielectric thickness (expressed in terms of equivalent SiO2 thickness or teq) to fall below 1.5nm in the 100nm generation by 2005. In the case of the gate dielectric, leakage current increases exponentially as SiO2 thickness is reduced below 4nm [1]. Thinner oxides also produce larger fields for a given bias, accelerating the onset of dielectric breakdown. In the case of capacitors used for DRAMs, higher leakage current reduces retention times. By using materials with a higher dielectric constant, k, a small teq can be achieved using dielectric layers with a larger physical thickness, tp. The scaling in thickness is inversely related to the scaling in the dielectric constant: teq = (kSiO2 / k) * tp K2.2.1
The value of kSiO2 is 3.9. The use of oxynitride mater
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